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PIC16F913/914/916/917/946 Data Sheet
28/40/44/64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology
(c) 2007 Microchip Technology Inc.
DS41250F
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS41250F-page ii
(c) 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946
28/40/44/64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology
High-Performance RISC CPU:
* Only 35 instructions to learn: - All single-cycle instructions except branches * Operating speed: - DC - 20 MHz oscillator/clock input - DC - 200 ns instruction cycle * Program Memory Read (PMR) capability * Interrupt capability * 8-level deep hardware stack * Direct, Indirect and Relative Addressing modes
Low-Power Features:
* Standby Current: - <100 nA @ 2.0V, typical * Operating Current: - 11 A @ 32 kHz, 2.0V, typical - 220 A @ 4 MHz, 2.0V, typical * Watchdog Timer Current: - 1 A @ 2.0V, typical
Peripheral Features:
* Liquid Crystal Display module: - Up to 60/96/168 pixel drive capability on 28/40/64-pin devices, respectively - Four commons * Up to 24/35/53 I/O pins and 1 input-only pin: - High-current source/sink for direct LED drive - Interrupt-on-change pin - Individually programmable weak pull-ups * In-Circuit Serial ProgrammingTM (ICSPTM) via two pins * Analog comparator module with: - Two analog comparators - Programmable on-chip voltage reference (CVREF) module (% of VDD) - Comparator inputs and outputs externally accessible * A/D Converter: - 10-bit resolution and up to 8 channels * Timer0: 8-bit timer/counter with 8-bit programmable prescaler * Enhanced Timer1: - 16-bit timer/counter with prescaler - External Timer1 Gate (count enable) - Option to use OSC1 and OSC2 as Timer1 oscillator if INTOSCIO or LP mode is selected * Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler * Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) * Up to 2 Capture, Compare, PWM modules: - 16-bit Capture, max. resolution 12.5 ns - 16-bit Compare, max. resolution 200 ns - 10-bit PWM, max. frequency 20 kHz * Synchronous Serial Port (SSP) with I2CTM
Special Microcontroller Features:
* Precision Internal Oscillator: - Factory calibrated to 1%, typical - Software selectable frequency range of 8 MHz to 125 kHz - Software tunable - Two-Speed Start-up mode - External Oscillator fail detect for critical applications - Clock mode switching during operation for power savings * Software selectable 31 kHz internal oscillator * Power-Saving Sleep mode * Wide operating voltage range (2.0V-5.5V) * Industrial and Extended temperature range * Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Brown-out Reset (BOR) with software control option * Enhanced Low-Current Watchdog Timer (WDT) with on-chip oscillator (software selectable nominal 268 seconds with full prescaler) with software enable * Multiplexed Master Clear with pull-up/input pin * Programmable code protection * High-Endurance Flash/EEPROM cell: - 100,000 write Flash endurance - 1,000,000 write EEPROM endurance - Flash/Data EEPROM retention: > 40 years
(c) 2007 Microchip Technology Inc.
DS41250F-page 1
PIC16F913/914/916/917/946
Program Memory Flash (words/bytes) 4K/7K 4K/7K 8K/14K 8K/14K 8K/14K Data Memory SRAM (bytes) 256 256 352 352 336 EEPROM (bytes) 256 256 256 256 256 I/O LCD (segment drivers) 16(1) 24 16(1) 24 42
Device
10-bit A/D (ch) 5 8 5 8 8
CCP
Timers 8/16-bit 2/1 2/1 2/1 2/1 2/1
PIC16F913 PIC16F914 PIC16F916 PIC16F917 PIC16F946 Note 1:
24 35 24 35 53
1 2 1 2 2
COM3 and SEG15 share the same physical pin on the PIC16F913/916, therefore SEG15 is not available when using 1/4 multiplex displays.
Pin Diagrams - PIC16F914/917, 40-Pin
40-pin PDIP
RE3/MCLR/VPP RA0/AN0/C1-/SEG12 RA1/AN1/C2-/SEG7 RA2/AN2/C2+/VREF-/COM2 RA3/AN3/C1+/VREF+/SEG15 RA4/C1OUT/T0CKI/SEG4 RA5/AN4/C2OUT/SS/SEG5 RE0/AN5/SEG21 RE1/AN6/SEG22 RE2/AN7/SEG23 VDD VSS RA7/OSC1/CLKIN/T1OSI RA6/OSC2/CLKOUT/T1OSO RC0/VLCD1 RC1/VLCD2 RC2/VLCD3 RC3/SEG6 RD0/COM3 RD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7/ICSPDAT/ICDDAT/SEG13 RB6/ICSPCLK/ICDCK/SEG14 RB5/COM1 RB4/COM0 RB3/SEG3 RB2/SEG2 RB1/SEG1 RB0/INT/SEG0 VDD VSS RD7/SEG20 RD6/SEG19 RD5/SEG18 RD4/SEG17 RC7/RX/DT/SDI/SDA/SEG8 RC6/TX/CK/SCK/SCL/SEG9 RC5/T1CKI/CCP1/SEG10 RC4/T1G/SDO/SEG11 RD3/SEG16 RD2/CCP2
PIC16F914/917
DS41250F-page 2
(c) 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946
TABLE 1:
I/O RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RE0 RE1 RE2 RE3 -- -- -- -- Note Pin 2 3 4 5 6 7 14 13 33 34 35 36 37 38 39 40 15 16 17 18 23 24 25 26 19 20 21 22 27 28 29 30 8 9 10 1 11 32 12 31 1: AN4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- AN5 AN6 AN7 -- -- -- -- --
PIC16F914/917 40-PIN SUMMARY
A/D AN0 AN1 AN2/VREFAN3/VREF+ LCD SEG12 SEG7 COM2 SEG15 SEG4 SEG5 -- -- SEG0 SEG1 SEG2 SEG3 COM0 COM1 SEG14 SEG13 VLCD1 VLCD2 VLCD3 SEG6 SEG11 SEG10 SEG9 SEG8 COM3 -- -- SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 -- -- -- -- -- Comparators C1C2C2+ C1+ C1OUT C2OUT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Timers -- -- -- -- T0CKI -- T1OSO T1OSI -- -- -- -- -- -- -- -- -- -- -- -- T1G T1CKI -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CCP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CCP1 -- -- -- -- CCP2 -- -- -- -- -- -- -- -- -- -- -- -- -- AUSART -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TX/CK RX/DT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SSP -- -- -- -- -- SS -- -- -- -- -- -- -- -- -- -- -- -- -- -- SDO -- SCK/SCL SDI/SDA -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Interrupt -- -- -- -- -- -- -- -- INT -- -- -- IOC IOC IOC IOC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pull-Up -- -- -- -- -- -- -- -- Y Y Y Y Y Y Y Y -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Y(1) -- -- -- -- Basic -- -- -- -- -- -- OSC2/CLKOUT OSC1/CLKIN -- -- -- -- -- -- ICSPCLK/ICDCK ICSPDAT/ICDDAT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MCLR/VPP VDD VDD VSS VSS
Pull-up enabled only with external MCLR configuration.
(c) 2007 Microchip Technology Inc.
DS41250F-page 3
PIC16F913/914/916/917/946
Pin Diagrams - PIC16F913/916, 28-Pin
28-pin PDIP, SOIC, SSOP
RE3/MCLR/VPP RA0/AN0/C1-/SEG12 RA1/AN1/C2-/SEG7 RA2/AN2/C2+/VREF-/COM2 RA3/AN3/C1+/VREF+/COM3/SEG15 RA4/C1OUT/T0CKI/SEG4 RA5/AN4/C2OUT/SS/SEG5 VSS RA7/OSC1/CLKIN/T1OSI RA6/OSC2/CLKOUT/T1OSO RC0/VLCD1 RC1/VLCD2 RC2/VLCD3 RC3/SEG6
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
RB7/ICSPDAT/ICDDAT/SEG13 RB6/ICSPCLK/ICDCK/SEG14 RB5/COM1 RB4/COM0 RB3/SEG3 RB2/SEG2 RB1/SEG1 RB0/INT/SEG0 VDD VSS RC7/RX/DT/SDI/SDA/SEG8 RC6/TX/CK/SCK/SCL/SEG9 RC5/T1CKI/CCP1/SEG10 RC4/T1G/SDO/SEG11
RB7/ICSPDAT/ICDDAT/SEG13
RB6/ICSPCLK/ICDCK/SEG14
28-pin QFN
RA0/AN0/C1-/SEG12
RA1/AN1/C2-/SEG7
RE3/MCLR/VPP
PIC16F913/916 RB5/COM1
28 27
26 25 24 23
22
RB4/COM0
RA2/AN2/C2+/VREF-/COM2 RA3/AN3/C1+/VREF+/COM3/SEG15 RA4/C1OUT/T0CKI/SEG4 RA5/AN4/C2OUT/SS/SEG5 VSS RA7/OSC1/CLKIN/T1OSI RA6/OSC2/CLKOUT/T1OSO
1 2 3 4 5 6 7
21 20 19 18 17 16 15
RB3/SEG3 RB2/SEG2 RB1/SEG1 RB0/INT/SEG0 VDD VSS RC7/RX/DT/SDI/SDA/SEG8
PIC16F913/916
10
11
12 RC4/T1G/SDO/SEG11
13 RC5/T1CKI/CCP1/SEG10
RC6/TX/CK/SCK/SCL/SEG9
RC0/VLCD1
RC1/VLCD2
RC2/VLCD3
RC3/SEG6
14
8
9
DS41250F-page 4
(c) 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946
TABLE 2:
I/O RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RE3 -- -- -- Note 1: Pin 2 3 4 5 6 7 10 9 21 22 23 24 25 26 27 28 11 12 13 14 15 16 17 18 1 20 8 19
PIC16F913/916 28-PIN (PDIP, SOIC, SSOP) SUMMARY
A/D AN0 AN1 AN2/VREFAN3/VREF+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- LCD SEG12 SEG7 COM2 SEG15/ COM3 SEG4 SEG5 -- -- SEG0 SEG1 SEG2 SEG3 COM0 COM1 SEG14 SEG13 VLCD1 VLCD2 VLCD3 SEG6 SEG11 SEG10 SEG9 SEG8 -- -- -- -- Comparators C1C2C2+ C1+ C1OUT C2OUT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Timers -- -- -- -- T0CKI -- T1OSO T1OSI -- -- -- -- -- -- -- -- -- -- -- -- T1G T1CKI -- -- -- -- -- -- CCP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CCP1 -- -- -- -- -- -- AUSART -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TX/CK RX/DT -- -- -- -- SSP -- -- -- -- -- SS -- -- -- -- -- -- -- -- -- -- -- -- -- -- SDO -- SCK/SCL SDI/SDA -- -- -- -- Interrupt -- -- -- -- -- -- -- -- INT -- -- -- IOC IOC IOC IOC -- -- -- -- -- -- -- -- -- -- -- -- Pull-Up -- -- -- -- -- -- -- -- Y Y Y Y Y Y Y Y -- -- -- -- -- -- -- -- Y(1) -- -- -- Basic -- -- -- -- -- -- OSC2/CLKOUT OSC1/CLKIN -- -- -- -- -- -- ICSPCLK/ICDCK ICSPDAT/ICDDAT -- -- -- -- -- -- -- -- MCLR/VPP VDD VSS VSS
Pull-up enabled only with external MCLR configuration.
(c) 2007 Microchip Technology Inc.
DS41250F-page 5
PIC16F913/914/916/917/946
TABLE 3:
I/O RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RE3 -- -- -- Note 1: Pin 27 28 1 2 3 4 7 6 18 19 20 21 22 23 24 25 8 9 10 11 12 13 14 15 26 17 5 16
PIC16F913/916 28-PIN (QFN) SUMMARY
A/D AN0 AN1 AN2/VREFAN3/VREF+ -- AN4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- LCD SEG12 SEG7 COM2 SEG15/ COM3 SEG4 SEG5 -- -- SEG0 SEG1 SEG2 SEG3 COM0 COM1 SEG14 SEG13 VLCD1 VLCD2 VLCD3 SEG6 SEG11 SEG10 SEG9 SEG8 -- -- -- -- Comparators C1C2C2+ C1+ C1OUT C2OUT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Timers -- -- -- -- T0CKI -- T1OSO T1OSI -- -- -- -- -- -- -- -- -- -- -- -- T1G T1CKI -- -- -- -- -- -- CCP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CCP1 -- -- -- -- -- -- AUSART -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TX/CK RX/DT -- -- -- -- SSP -- -- -- -- -- SS -- -- -- -- -- -- -- -- -- -- -- -- -- -- SDO -- SCK/SCL SDI/SDA -- -- -- -- Interrupt -- -- -- -- -- -- -- -- INT -- -- -- IOC IOC IOC IOC -- -- -- -- -- -- -- -- -- -- -- -- Pull-Up -- -- -- -- -- -- -- -- Y Y Y Y Y Y Y Y -- -- -- -- -- -- -- -- Y(1) -- -- -- Basic -- -- -- -- -- -- OSC2/CLKOUT OSC1/CLKIN -- -- -- -- -- -- ICSPCLK/ICDCK ICSPDAT/ICDDAT -- -- -- -- -- -- -- -- MCLR/VPP VDD VSS VSS
Pull-up enabled only with external MCLR configuration.
DS41250F-page 6
(c) 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946
Pin Diagrams - PIC16F914/917, 44-Pin
RC6/TX/CK/SCK/SCL/SEG9 RC5/T1CKI/CCP1/SEG10 RC4/T1G/SDO/SEG11 RD3/SEG16 RD2/CCP2 RD1 RD0/COM3 RC3/SEG6 RC2/VLCD3 RC1/VLCD2 NC 44 43 42 41 40 39 38 37 36 35 34
44-pin TQFP
NC NC RB4/COM0 RB5/COM1 RB6/ICSPCLK/ICDCK/SEG14 RB7/ICSPDAT/ICDDAT/SEG13 RE3/MCLR/VPP RA0/C1-/AN0/SEG12 RA1/C2-/AN1/SEG7 RA2/AN2/C2+/VREF-/COM2 RA3/AN3/VREF+/C1+/SEG15
12 13 14 15 16 17 18 19 20 21 22
RC7/RX/DT/SDI/SDA/SEG8 RD4/SEG17 RD5/SEG18 RD6/SEG19 RD7/SEG20 VSS VDD RB0/SEG0/INT RB1/SEG1 RB2/SEG2 RB3/SEG3
1 2 3 4 5 6 7 8 9 10 11
PIC16F914/917
33 32 31 30 29 28 27 26 25 24 23
NC RC0/VLCD1 RA6/OSC2/CLKOUT/T1OSO RA7/OSC1/CLKIN/T1OSI VSS VDD RE2/AN7/SEG23 RE1/AN6/SEG22 RE0/AN5/SEG21 RA5/AN4/C2OUT/SS/SEG5 RA4/C1OUT/T0CKI/SEG4
44-pin QFN
44 43 42 41 40 39 38 37 36 35 34
RC6/TX/CK/SCK/SCL/SEG9 RC5/T1CKI/CCP1/SEG10 RC4/T1G/SDO/SEG11 RD3/SEG16 RD2/CCP2 RD1 RD0/COM3 RC3/SEG6 RC2/VLCD3 RC1/VLCD2 RC0/VLDC1
(c) 2007 Microchip Technology Inc.
RB3/SEG3 NC RB4/COM0 RB5/COM1 RB6/ICSPCLK/ICDCK/SEG14 RB7/ICSPDAT/ICDDAT/SEG13 RE3/MCLR/VPP RA0/AN0/C1-/SEG12 RA1/AN1/C2-/SEG7 RA2/AN2/C2+/VREF-/COM2 RA3/AN3/C1+/VREF+/SEG15
12 13 14 15 16 17 18 19 20 21 22
RC7/RX/DT/SDI/SDA/SEG8 RD4/SEG17 RD5/SEG18 RD6/SEG19 RD7/SEG20 VSS VDD VDD RB0/INT/SEG0 RB1/SEG1 RB2/SEG2
1 2 3 4 5 6 7 8 9 10 11
PIC16F914/917
33 32 31 30 29 28 27 26 25 24 23
RA6/OSC2/CLKOUT/T1OSO RA7/OSC1/CLKIN/T1OSI VSS VSS NC VDD RE2/AN7/SEG23 RE1/AN6/SEG22 RE0/AN5/SEG21 RA5/AN4/C2OUT/SS/SEG5 RA4/C1OUT/T0CKI/SEG4
DS41250F-page 7
PIC16F913/914/916/917/946
TABLE 4:
I/O RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RE0 RE1 RE2 RE3 -- -- -- -- -- -- -- -- Note Pin 19 20 21 22 23 24 31 30 8 9 10 11 14 15 16 17 32 35 36 37 42 43 44 1 38 39 40 41 2 3 4 5 25 26 27 18 7 28 6 29 12 13 33 34 1:
PIC16F914/917 44-PIN (TQFP) SUMMARY
A/D AN0 AN1 AN2/VREFAN3/VREF+ -- AN4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- AN5 AN6 AN7 -- -- -- -- -- -- -- -- -- LCD SEG12 SEG7 COM2 SEG15 SEG4 SEG5 -- -- SEG0 SEG1 SEG2 SEG3 COM0 COM1 SEG14 SEG13 VLCD1 VLCD2 VLCD3 SEG6 SEG11 SEG10 SEG9 SEG8 COM3 -- -- SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 -- -- -- -- -- -- -- -- -- Comparators C1C2C2+ C1+ C1OUT C2OUT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Timers -- -- -- -- T0CKI -- T1OSO T1OSI -- -- -- -- -- -- -- -- -- -- -- -- T1G T1CKI -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CCP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CCP1 -- -- -- -- CCP2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- AUSART -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TX/CK RX/DT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SSP -- -- -- -- -- SS -- -- -- -- -- -- -- -- -- -- -- -- -- -- SDO -- SCK/SCL SDI/SDA -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Interrupt -- -- -- -- -- -- -- -- INT -- -- -- IOC IOC IOC IOC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pull-Up -- -- -- -- -- -- -- -- Y Y Y Y Y Y Y Y -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Y(1) -- -- -- -- -- -- -- -- Basic -- -- -- -- -- -- OSC2/CLKOUT OSC1/CLKIN -- -- -- -- -- -- ICSPCLK/ICDCK ICSPDAT/ICDDAT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MCLR/VPP VDD VDD VSS VSS NC NC NC NC
Pull-up enabled only with external MCLR configuration.
DS41250F-page 8
(c) 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946
TABLE 5:
I/O RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RE0 RE1 RE2 RE3 -- -- -- -- -- -- -- Note Pin 19 20 21 22 23 24 33 32 9 10 11 12 14 15 16 17 34 35 36 37 42 43 44 1 38 39 40 41 2 3 4 5 25 26 27 18 7 8 28 6 30 13 29 1:
PIC16F914/917 44-PIN (QFN) SUMMARY
A/D AN0 AN1 AN2/VREFAN3/VREF+ -- AN4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- AN5 AN6 AN7 -- -- -- -- -- -- -- -- LCD SEG12 SEG7 COM2 SEG15 SEG4 SEG5 -- -- SEG0 SEG1 SEG2 SEG3 COM0 COM1 SEG14 SEG13 VLCD1 VLCD2 VLCD3 SEG6 SEG11 SEG10 SEG9 SEG8 COM3 -- -- SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 -- -- -- -- -- -- -- -- Comparators C1C2C2+ C1+ C1OUT C2OUT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Timers -- -- -- -- T0CKI -- T1OSO T1OSI -- -- -- -- -- -- -- -- -- -- -- -- T1G T1CKI -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CCP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CCP1 -- -- -- -- CCP2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- AUSART -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TX/CK RX/DT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SSP -- -- -- -- -- SS -- -- -- -- -- -- -- -- -- -- -- -- -- -- SDO -- SCK/SCL SDI/SDA -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Interrupt -- -- -- -- -- -- -- -- INT -- -- -- IOC IOC IOC IOC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pull-Up -- -- -- -- -- -- -- -- Y Y Y Y Y Y Y Y -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Y(1) -- -- -- -- -- -- -- Basic -- -- -- -- -- -- OSC2/CLKOUT OSC1/CLKIN -- -- -- -- -- -- ICSPCLK/ICDCK ICSPDAT/ICDDAT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MCLR/VPP VDD VDD VDD VSS VSS NC NC
Pull-up enabled only with external MCLR configuration.
(c) 2007 Microchip Technology Inc.
DS41250F-page 9
PIC16F913/914/916/917/946
Pin Diagram - PIC16F946
RC6/TX/CK/SCK/SCL/SEG9 RC7/RX/DT/SDI/SDA/SEG8
RC5/T1CKI/CCP1/SEG10
64-pin TQFP
RD5/SEG18 RD4/SEG17
RC4/T1G/SDO/SEG11
RD3/SEG16
RC2/VLCD3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RC1/VLCD2
RD0/COM3
RC3/SEG6
RD2/CCP2
RD1
VSS
RC0/VLCD1
VDD
RD6/SEG19 RD7/SEG20 RG0/SEG36 RG1/SEG37 RG2/SEG38 RG3/SEG39 RG4/SEG40 RG5/SEG41 VSS VDD RF0/SEG32 RF1/SEG33 RF2/SEG34 RF3/SEG35 RB0/INT/SEG0 RB1/SEG1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
RF7/SEG31 RF6/SEG30 RF5/SEG29 RF4/SEG28 RE7/SEG27 RE6/SEG26 RE5/SEG25 VSS RA6/OSC2/CLKOUT/T1OSO RA7/OSC1/CLKIN/T1OSI VDD RE4/SEG24 RE3/MCLR/VPP RE2/AN7/SEG23 RE1/AN6/SEG22 RE0/AN5/SEG21
PIC16F946
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RB7/ICSPDAT/ICDDAT/SEG13 AVSS
RB3/SEG3 VDD
RB5/COM1 RB6/ICSPCLK/ICDCK/SEG14
RA2/AN2/C2+/VREF-/COM2 RA3/AN3/C1+/VREF+/SEG15
RA5/AN4/C2OUT/SS/SEG5
RB2/SEG2
RB4/COM0
RA1/AN1/C2-/SEG7
RA4/C1OUT/T0CKI/SEG4
AVDD
RA0/AN0/C1-/SEG12
VSS
DS41250F-page 10
(c) 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946
TABLE 6:
I/O RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7 RF0 RF1 RF2 Note Pin 27 28 29 30 31 32 40 39 15 16 17 18 21 22 23 24 49 50 51 52 59 60 61 62 53 54 55 58 63 64 1 2 33 34 35 36 37 42 43 44 11 12 13 1:
PIC16F946 64-PIN (TQFP) SUMMARY
A/D AN0 AN1 AN2/VREFAN3/VREF+ -- AN4 SEG5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- AN5 AN6 AN7 -- -- -- -- -- -- -- -- LCD SEG12 SEG7 COM2 SEG15 SEG4 -- -- -- SEG0 SEG1 SEG2 SEG3 COM0 COM1 SEG14 SEG13 VLCD1 VLCD2 VLCD3 SEG6 SEG11 SEG10 SEG9 SEG8 COM3 -- -- SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 -- SEG24 SEG25 SEG26 SEG27 SEG32 SEG33 SEG34 Comparators C1C2C2+ C1+ C1OUT C2OUT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Timers -- -- -- -- T0CKI -- T1OSO T1OSI -- -- -- -- -- -- -- -- -- -- -- -- T1G T1CKI -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CCP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CCP1 -- -- -- -- CCP2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- AUSART -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TX/CK RX/DT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SSP -- -- -- -- -- SS -- -- -- -- -- -- -- -- -- -- -- -- -- -- SDO -- SCK/SCL SDI/SDA -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Interrupt -- -- -- -- -- -- -- -- INT -- -- -- IOC IOC IOC IOC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pull-Up -- -- -- -- -- -- -- -- Y Y Y Y Y Y Y Y -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Y(1) -- -- -- -- -- -- -- Basic -- -- -- -- -- -- OSC2/CLKOUT OSC1/CLKIN -- -- -- -- -- -- ICSPCLK/ICDCK ICSPDAT/ICDDAT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MCLR/VPP -- -- -- -- -- -- --
Pull-up enabled only with external MCLR configuration.
(c) 2007 Microchip Technology Inc.
DS41250F-page 11
PIC16F913/914/916/917/946
TABLE 6:
I/O RF3 RF4 RF5 RF6 RF7 RG0 RG1 RG2 RG3 RG4 RG5 -- -- -- -- -- -- -- -- -- -- Note Pin 14 45 46 47 48 3 4 5 6 7 8 26 25 10 19 38 57 9 20 41 56 1: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
PIC16F946 64-PIN (TQFP) SUMMARY (CONTINUED)
A/D LCD SEG35 SEG28 SEG29 SEG30 SEG31 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 -- -- -- -- -- -- -- -- -- -- Comparators -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Timers -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CCP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- AUSART -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SSP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Interrupt -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pull-Up -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Basic -- -- -- -- -- -- -- -- -- -- -- AVDD AVSS VDD VDD VDD VDD VSS VSS VSS VSS
Pull-up enabled only with external MCLR configuration.
DS41250F-page 12
(c) 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 15 2.0 Memory Organization ................................................................................................................................................................. 23 3.0 I/O Ports ..................................................................................................................................................................................... 43 4.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 87 5.0 Timer0 Module ........................................................................................................................................................................... 99 6.0 Timer1 Module with Gate Control............................................................................................................................................. 102 7.0 Timer2 Module ......................................................................................................................................................................... 107 8.0 Comparator Module.................................................................................................................................................................. 109 9.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) ........................................................... 121 10.0 Liquid Crystal Display (LCD) Driver Module............................................................................................................................. 143 11.0 Programmable Low-Voltage Detect (PLVD) Module................................................................................................................ 171 12.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 175 13.0 Data EEPROM and Flash Program Memory Control ............................................................................................................... 187 14.0 SSP Module Overview ............................................................................................................................................................. 193 15.0 Capture/Compare/PWM (CCP) Module ................................................................................................................................... 211 16.0 Special Features of the CPU.................................................................................................................................................... 219 17.0 Instruction Set Summary .......................................................................................................................................................... 241 18.0 Development Support............................................................................................................................................................... 251 19.0 Electrical Specifications............................................................................................................................................................ 255 20.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 283 21.0 Packaging Information.............................................................................................................................................................. 305 Appendix A: Data Sheet Revision History.......................................................................................................................................... 315 Appendix B: Migrating From Other PIC(R) Devices.............................................................................................................................. 315 Appendix C: Conversion Considerations ........................................................................................................................................... 316 Index .................................................................................................................................................................................................. 317 The Microchip Web Site ..................................................................................................................................................................... 325 Customer Change Notification Service .............................................................................................................................................. 325 Customer Support .............................................................................................................................................................................. 325 Reader Response .............................................................................................................................................................................. 327 Product Identification System ............................................................................................................................................................ 328
TO OUR VALUED CUSTOMERS
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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(c) 2007 Microchip Technology Inc.
DS41250F-page 13
PIC16F913/914/916/917/946
NOTES:
DS41250F-page 14
(c) 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946
1.0 DEVICE OVERVIEW
The PIC16F91X/946 devices are covered by this data sheet. They are available in 28/40/44/64-pin packages. Figure 1-1 shows a block diagram of the PIC16F913/916 device, Figure 1-2 shows a block diagram of the PIC16F914/917 device, and Figure 1-3 shows a block diagram of the PIC16F946 device. Table 1-1 shows the pinout descriptions.
FIGURE 1-1:
PIC16F913/916 BLOCK DIAGRAM
INT Configuration 13 Program Counter Flash 4K/8K x 14 Program Memory 8-Level Stack (13-bit) RAM 256/352 bytes File Registers 9 RAM Addr PORTB RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 PORTC 3 Instruction Decode and Control
Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset
Data Bus
8
PORTA RA0 RA1 RA2 RA3 RA4 RA5 RA7
Program 14 Bus Instruction Reg
Program Memory Read (PMR)
Addr MUX Direct Addr 7 8 Indirect Addr
FSR Reg STATUS Reg
8
MUX
ALU 8 W Reg PORTE
OSC1/CLKIN OSC2/CLKOUT Timing Generation
RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7
Internal Oscillator Block VDD VSS
RE3/MCLR
Data EEPROM 256 bytes Timer0 Timer1 Timer2 10-bit A/D
Comparators
CCP1
SSP
Addressable USART
PLVD
LCD
(c) 2007 Microchip Technology Inc.
DS41250F-page 15
PIC16F913/914/916/917/946
FIGURE 1-2: PIC16F914/917 BLOCK DIAGRAM
INT Configuration 13 Program Counter Flash 4K/8K x 14 Program Memory Program 14 Bus Instruction Reg Direct Addr 7 8-Level Stack (13-bit) RAM 256/352 bytes File Registers 9 RAM Addr PORTB RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 PORTC 3 Instruction Decode and Control OSC1/CLKIN OSC2/CLKOUT Timing Generation
Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset
Data Bus
8
PORTA RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7
Program Memory Read (PMR)
Addr MUX 8 Indirect Addr
FSR Reg STATUS Reg
8
MUX
ALU 8 W Reg PORTD
RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7
Internal Oscillator Block VDD VSS PORTE
RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7
RE0 RE1 RE2 RE3/MCLR
Timer0
Timer1
Timer2
10-bit A/D
Data EEPROM 256 bytes
Comparators
CCP1
CCP2
SSP
Addressable USART
PLVD
LCD
DS41250F-page 16
(c) 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946
FIGURE 1-3: PIC16F946 BLOCK DIAGRAM
INT Configuration 13 Program Counter Flash 8K x 14 Program Memory Program 14 Bus Instruction Reg Direct Addr 7 8-Level Stack (13-bit) RAM 336 x 8 bytes File Registers 9 RAM Addr Data Bus 8 PORTA RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 PORTB RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 PORTC RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 PORTD ALU 8 W Reg RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 PORTE VDD VSS RE0 RE1 RE2 RE3/MCLR RE4 RE5 RE6 RE7 PORTF RF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7 PORTG RG0 RG1 RG2 RG3 RG4 RG5 Data EEPROM 256 bytes
Program Memory Read (PMR)
Addr MUX 8 Indirect Addr
FSR Reg 8 STATUS Reg
Power-up Timer
3
MUX
Instruction Decode and Control OSC1/CLKIN OSC2/CLKOUT Timing Generation
Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset
Internal Oscillator Block
AVDD AVSS
Timer0
Timer1
Timer2
10-bit A/D
Comparators
CCP1
CCP2
SSP
Addressable USART
PLVD
LCD
(c) 2007 Microchip Technology Inc.
DS41250F-page 17
PIC16F913/914/916/917/946
TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS
Function
RA0 AN0 C1SEG12 RA1/AN1/C2-/SEG7 RA1 AN1 C2SEG7 RA2/AN2/C2+/VREF-/COM2 RA2 AN2 C2+ VREFCOM2 RA3/AN3/C1+/VREF+/COM3(1)/ SEG15 RA3 AN3 C1+ VREF+ COM3(1) SEG15 RA4/C1OUT/T0CKI/SEG4 RA4 C1OUT T0CKI SEG4 RA5/AN4/C2OUT/SS/SEG5 RA5 AN4 C2OUT SS SEG5 RA6/OSC2/CLKOUT/T1OSO RA6 OSC2 CLKOUT T1OSO RA7/OSC1/CLKIN/T1OSI RA7 OSC1 CLKIN T1OSI RB0/INT/SEG0 RB0 INT SEG0 Legend: AN = Analog input or output TTL = TTL compatible input HV = High Voltage
Name
RA0/AN0/C1-/SEG12
Input Output Type Type
TTL AN AN -- TTL AN AN -- TTL AN AN AN -- TTL AN AN AN -- -- TTL -- ST -- TTL AN -- TTL -- TTL -- -- -- TTL XTAL ST XTAL TTL ST -- CMOS General purpose I/O. -- -- AN -- -- AN -- -- -- AN -- -- -- AN AN
Description
Analog input Channel 0. Comparator 1 negative input. LCD analog output. Analog input Channel 1. Comparator 2 negative input. LCD analog output. Analog input Channel 2. Comparator 2 positive input. External A/D Voltage Reference - negative. LCD analog output. Analog input Channel 3. Comparator 1 positive input. External A/D Voltage Reference - positive. LCD analog output. LCD analog output.
CMOS General purpose I/O.
CMOS General purpose I/O.
CMOS General purpose I/O.
CMOS General purpose I/O. CMOS Comparator 1 output. -- AN -- -- AN XTAL XTAL -- -- -- -- AN Timer0 clock input. LCD analog output. Analog input Channel 4. Slave select input. LCD analog output. Crystal/Resonator. Timer1 oscillator output. Crystal/Resonator. Clock input. Timer1 oscillator input. External interrupt pin. LCD analog output.
CMOS General purpose I/O. CMOS Comparator 2 output.
CMOS General purpose I/O. CMOS TOSC/4 reference clock. CMOS General purpose I/O.
CMOS General purpose I/O. Individually enabled pull-up.
CMOS = CMOS compatible input or output OD = Open Drain ST = Schmitt Trigger input with CMOS levels P = Power XTAL = Crystal
Note 1: 2: 3: 4:
COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946. Pins available on PIC16F914/917 and PIC16F946 only. Pins available on PIC16F946 only. I2C Schmitt trigger inputs have special input levels.
DS41250F-page 18
(c) 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946
TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS (CONTINUED)
Function
RB1 SEG1 RB2/SEG2 RB3/SEG3 RB4/COM0 RB2 SEG2 RB3 SEG3 RB4 COM0 RB5/COM1 RB5 COM1 RB6/ICSPCLK/ICDCK/SEG14 RB6 ICSPCLK ICDCK SEG14 RB7/ICSPDAT/ICDDAT/SEG13 RB7 ICSPDAT ICDDAT SEG13 RC0/VLCD1 RC1/VLCD2 RC2/VLCD3 RC3/SEG6 RC4/T1G/SDO/SEG11 RC0 VLCD1 RC1 VLCD2 RC2 VLCD3 RC3 SEG6 RC4 T1G SDO SEG11 RC5/T1CKI/CCP1/SEG10 RC5 T1CKI CCP1 SEG10 Legend: AN = Analog input or output TTL = TTL compatible input HV = High Voltage
Name
RB1/SEG1
Input Output Type Type
TTL -- TTL -- TTL -- TTL -- TTL -- TTL ST ST -- TTL ST ST -- ST AN ST AN ST AN ST -- ST ST -- -- ST ST ST -- AN AN AN LCD analog output. LCD analog output. LCD analog output.
Description
CMOS General purpose I/O. Individually enabled pull-up. CMOS General purpose I/O. Individually enabled pull-up. CMOS General purpose I/O. Individually enabled pull-up. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN LCD analog output. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN LCD analog output. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. -- -- AN ICSPTM clock. ICD clock. LCD analog output.
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. CMOS ICSP Data I/O. CMOS ICD Data I/O. AN -- -- -- AN -- AN -- AN LCD analog output. LCD analog input. LCD analog input. LCD analog input. LCD analog output. Timer1 gate input. LCD analog output. Timer1 clock input. LCD analog output. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS Serial data output. CMOS General purpose I/O. CMOS Capture 1 input/Compare 1 output/PWM 1 output.
CMOS = CMOS compatible input or output OD = Open Drain ST = Schmitt Trigger input with CMOS levels P = Power XTAL = Crystal
Note 1: 2: 3: 4:
COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946. Pins available on PIC16F914/917 and PIC16F946 only. Pins available on PIC16F946 only. I2C Schmitt trigger inputs have special input levels.
(c) 2007 Microchip Technology Inc.
DS41250F-page 19
PIC16F913/914/916/917/946
TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS (CONTINUED)
Function
RC6 TX CK SCK SCL SEG9 RC7/RX/DT/SDI/SDA/SEG8 RC7 RX DT SDI SDA SEG8 RD0/COM3(1, 2) RD1(2) RD2/CCP2(2) RD3/SEG16(2) RD4/SEG17(2) RD5/SEG18 RD6/SEG19
(2)
Name
RC6/TX/CK/SCK/SCL/SEG9
Input Output Type Type
ST -- ST ST ST(4) -- ST ST ST ST ST
(4)
Description
CMOS General purpose I/O. CMOS USART asynchronous serial transmit. CMOS USART synchronous serial clock. CMOS SPI clock. OD AN -- I2CTM clock. LCD analog output. USART asynchronous serial receive.
CMOS General purpose I/O. CMOS USART synchronous serial data. CMOS SPI data input. OD AN AN I2CTM data. LCD analog output. LCD analog output.
-- ST -- ST ST ST ST -- ST -- ST -- ST -- ST -- ST AN -- ST AN -- ST AN -- ST ST HV
RD0 COM3 RD1 RD2 CCP2 RD3 SEG16 RD4 SEG17 RD5 SEG18 RD6 SEG19 RD7 SEG20 RE0 AN5 SEG21
CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS Capture 2 input/Compare 2 output/PWM 2 output. CMOS General purpose I/O. AN AN AN AN AN -- AN -- AN -- AN -- -- -- LCD analog output. LCD analog output. LCD analog output. LCD analog output. LCD analog output. Analog input Channel 5. LCD analog output. Analog input Channel 6. LCD analog output. Analog input Channel 7. LCD analog output. Digital input only. Master Clear with internal pull-up. Programming voltage. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O.
(2)
RD7/SEG20(2) RE0/AN5/SEG21(2)
RE1/AN6/SEG22(2)
RE1 AN6 SEG22
CMOS General purpose I/O.
RE2/AN7/SEG23(2)
RE2 AN7 SEG23
CMOS General purpose I/O.
RE3/MCLR/VPP
RE3 MCLR VPP
Legend:
AN = Analog input or output TTL = TTL compatible input HV = High Voltage
CMOS = CMOS compatible input or output OD = Open Drain ST = Schmitt Trigger input with CMOS levels P = Power XTAL = Crystal
Note 1: 2: 3: 4:
COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946. Pins available on PIC16F914/917 and PIC16F946 only. Pins available on PIC16F946 only. I2C Schmitt trigger inputs have special input levels.
DS41250F-page 20
(c) 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946
TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS (CONTINUED)
Function
RE4 SEG24 RE5/SEG25
(3)
Name
RE4/SEG24(3)
Input Output Type Type
ST -- ST -- ST -- ST -- ST -- ST -- ST -- ST -- ST -- ST -- ST -- ST -- ST -- ST -- ST -- ST -- ST -- ST -- P P P CMOS General purpose I/O. AN AN AN AN AN AN AN AN AN AN AN AN AN AN AN AN AN AN -- -- -- LCD analog output. LCD analog output. LCD analog output. LCD analog output. LCD analog output. LCD analog output. LCD analog output. LCD analog output. LCD analog output. LCD analog output. LCD analog output. LCD analog output. LCD analog output. LCD analog output. LCD analog output. LCD analog output. LCD analog output. LCD analog output. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O.
Description
RE5 SEG25 RE6 SEG26 RE7 SEG27 RF0 SEG32 RF1 SEG33 RF2 SEG34 RF3 SEG35 RF4 SEG28 RF5 SEG29 RF6 SEG30 RF7 SEG31 RG0 SEG36 RG1 SEG37 RG2 SEG38 RG3 SEG39 RG4 SEG10 RG5 SEG41 AVDD AVSS VDD
RE6/SEG26(3) RE7/SEG27(3) RF0/SEG32(3) RF1/SEG33
(3)
RF2/SEG34(3) RF3/SEG35(3) RF4/SEG28(3) RF5/SEG29
(3)
RF6/SEG30(3) RF7/SEG31(3) RG0/SEG36(3) RG1/SEG37
(3)
RG2/SEG38(3) RG3/SEG39(3) RG4/SEG40(3) RG5/SEG41 AVDD(3) AVSS(3) VDD Legend:
(3)
Analog power supply for microcontroller. Analog ground reference for microcontroller. Power supply for microcontroller.
AN = Analog input or output TTL = TTL compatible input HV = High Voltage
CMOS = CMOS compatible input or output OD = Open Drain ST = Schmitt Trigger input with CMOS levels P = Power XTAL = Crystal
Note 1: 2: 3: 4:
COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946. Pins available on PIC16F914/917 and PIC16F946 only. Pins available on PIC16F946 only. I2C Schmitt trigger inputs have special input levels.
(c) 2007 Microchip Technology Inc.
DS41250F-page 21
PIC16F913/914/916/917/946
TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS (CONTINUED)
Function
VSS AN = Analog input or output TTL = TTL compatible input HV = High Voltage
Name
VSS Legend:
Input Output Type Type
P --
Description
Ground reference for microcontroller.
CMOS = CMOS compatible input or output OD = Open Drain ST = Schmitt Trigger input with CMOS levels P = Power XTAL = Crystal
Note 1: 2: 3: 4:
COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946. Pins available on PIC16F914/917 and PIC16F946 only. Pins available on PIC16F946 only. I2C Schmitt trigger inputs have special input levels.
DS41250F-page 22
(c) 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946
2.0
2.1
MEMORY ORGANIZATION
Program Memory Organization
FIGURE 2-2:
PROGRAM MEMORY MAP AND STACK FOR THE PIC16F916/917/PIC16F946
pc<12:0>
The PIC16F91X/946 has a 13-bit program counter capable of addressing a 4K x 14 program memory space for the PIC16F913/914 (0000h-0FFFh) and an 8K x 14 program memory space for the PIC16F916/ 917 and PIC16F946 (0000h-1FFFh). Accessing a location above the memory boundaries for the PIC16F913 and PIC16F914 will cause a wrap around within the first 4K x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h.
CALL, RETURN RETFIE, RETLW
13
Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector Interrupt Vector Page 0 0000h 0004h 0005h 07FFh 0800h 0FFFh 1000h Page 2 17FFh 1800h 1FFFh
FIGURE 2-1:
PROGRAM MEMORY MAP AND STACK FOR THE PIC16F913/914
pc<12:0>
CALL, RETURN RETFIE, RETLW
13 On-chip Program Memory Page 1
Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector Interrupt Vector On-chip Program Memory Page 0 Page 1 07FFh 0800h 0FFFh 1000h 0000h 0004h 0005h
Page 3
1FFFh
(c) 2007 Microchip Technology Inc.
DS41250F-page 23
PIC16F913/914/916/917/946
2.2 Data Memory Organization
The data memory is partitioned into multiple banks which contain the General Purpose Registers (GPRs) and the Special Function Registers (SFRs). Bits RP0 and RP1 are bank select bits. RP1 0 0 1 1 RP0 0 1 0 1 Bank 0 is selected Bank 1 is selected Bank 2 is selected Bank 3 is selected
Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are the General Purpose Registers, implemented as static RAM. All implemented banks contain Special Function Registers. Some frequently used Special Function Registers from one bank are mirrored in another bank for code reduction and quicker access.
2.2.1
GENERAL PURPOSE REGISTER FILE
The register file is organized as 256 x 8 bits in the PIC16F913/914, 352 x 8 bits in the PIC16F916/917 and 336 x 8 bits in the PIC16F946. Each register is accessed either directly or indirectly through the File Select Register (FSR) (see Section 2.5 "Indirect Addressing, INDF and FSR Registers").
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Tables 2-1, 2-2, 2-3 and 2-4). These registers are static RAM. The Special Function Registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the "core" are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
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FIGURE 2-3: PIC16F913/916 SPECIAL FUNCTION REGISTERS
File Address (1) Indirect addr. 80h OPTION_REG 81h PCL 82h STATUS 83h FSR 84h TRISA 85h TRISB 86h TRISC 87h 88h TRISE 89h PCLATH 8Ah INTCON 8Bh PIE1 8Ch PIE2 8Dh PCON 8Eh OSCCON 8Fh OSCTUNE 90h ANSEL 91h PR2 92h SSPADD 93h SSPSTAT 94h WPUB 95h IOCB 96h CMCON1 97h TXSTA 98h SPBRG 99h 9Ah 9Bh CMCON0 9Ch VRCON 9Dh ADRESL 9Eh ADCON1 9Fh A0h General Purpose Register 80 Bytes accesses 70h-7Fh Bank 1 EFh F0h FFh File Address (1) Indirect addr. 100h TMR0 101h PCL 102h STATUS 103h FSR 104h WDTCON 105h PORTB 106h LCDCON 107h LCDPS 108h LVDCON 109h PCLATH 10Ah INTCON 10Bh EEDATL 10Ch EEADRL 10Dh EEDATH 10Eh EEADRH 10Fh LCDDATA0 110h LCDDATA1 111h 112h LCDDATA3 113h LCDDATA4 114h 115h LCDDATA6 116h LCDDATA7 117h 118h LCDDATA9 119h LCDDATA10 11Ah 11Bh LCDSE0 11Ch LCDSE1 11Dh 11Eh 11Fh 120h General Purpose Register 80 Bytes accesses 70h-7Fh Bank 2 16Fh 170h 17Fh accesses 70h-7Fh Bank 3 1EFh 1F0h 1FFh File Address (1) Indirect addr. 180h OPTION_REG 181h PCL 182h STATUS 183h FSR 184h 185h TRISB 186h 187h 188h 189h PCLATH 18Ah INTCON 18Bh EECON1 18Ch EECON2(1) 18Dh Reserved 18Eh Reserved 18Fh 190h File Address (1) Indirect addr. 00h TMR0 01h PCL 02h STATUS 03h FSR 04h PORTA 05h PORTB 06h PORTC 07h 08h PORTE 09h PCLATH 0Ah INTCON 0Bh PIR1 0Ch PIR2 0Dh TMR1L 0Eh TMR1H 0Fh T1CON 10h TMR2 11h T2CON 12h SSPBUF 13h SSPCON 14h CCPR1L 15h CCPR1H 16h CCP1CON 17h RCSTA 18h TXREG 19h RCREG 1Ah 1Bh 1Ch 1Dh ADRESH 1Eh ADCON0 1Fh 20h General Purpose Register 96 Bytes 7Fh Bank 0
General Purpose Register(2) 96 Bytes
Note 1: 2:
Unimplemented data memory locations, read as `0'. Not a physical register. On the PIC16F913, unimplemented data memory locations, read as `0'.
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FIGURE 2-4: PIC16F914/917 SPECIAL FUNCTION REGISTERS
File Address (1) Indirect addr. 80h OPTION_REG 81h PCL 82h STATUS 83h FSR 84h TRISA 85h TRISB 86h TRISC 87h TRISD 88h TRISE 89h PCLATH 8Ah INTCON 8Bh PIE1 8Ch PIE2 8Dh PCON 8Eh OSCCON 8Fh OSCTUNE 90h ANSEL 91h PR2 92h SSPADD 93h SSPSTAT 94h WPUB 95h IOCB 96h CMCON1 97h TXSTA 98h SPBRG 99h 9Ah 9Bh CMCON0 9Ch VRCON 9Dh ADRESL 9Eh ADCON1 9Fh A0h General Purpose Register 80 Bytes accesses 70h-7Fh Bank 1 EFh F0h FFh File Address (1) Indirect addr. 100h TMR0 101h PCL 102h STATUS 103h FSR 104h WDTCON 105h PORTB 106h LCDCON 107h LCDPS 108h LVDCON 109h PCLATH 10Ah INTCON 10Bh EEDATL 10Ch EEADRL 10Dh EEDATH 10Eh EEADRH 10Fh LCDDATA0 110h LCDDATA1 111h LCDDATA2 112h LCDDATA3 113h LCDDATA4 114h LCDDATA5 115h LCDDATA6 116h LCDDATA7 117h LCDDATA8 118h LCDDATA9 119h LCDDATA10 11Ah LCDDATA11 11Bh LCDSE0 11Ch LCDSE1 11Dh LCDSE2 11Eh 11Fh 120h General Purpose Register 80 Bytes accesses 70h-7Fh Bank 2 16Fh 170h 17Fh accesses 70h-7Fh Bank 3 1EFh 1F0h 1FFh File Address (1) Indirect addr. 180h OPTION_REG 181h PCL 182h STATUS 183h FSR 184h 185h TRISB 186h 187h 188h 189h PCLATH 18Ah INTCON 18Bh EECON1 18Ch EECON2(1) 18Dh Reserved 18Eh Reserved 18Fh 190h File Address (1) Indirect addr. 00h TMR0 01h PCL 02h STATUS 03h FSR 04h PORTA 05h PORTB 06h PORTC 07h PORTD 08h PORTE 09h PCLATH 0Ah INTCON 0Bh PIR1 0Ch PIR2 0Dh TMR1L 0Eh TMR1H 0Fh T1CON 10h TMR2 11h T2CON 12h SSPBUF 13h SSPCON 14h CCPR1L 15h CCPR1H 16h CCP1CON 17h RCSTA 18h TXREG 19h RCREG 1Ah CCPR2L 1Bh CCPR2H 1Ch CCP2CON 1Dh ADRESH 1Eh ADCON0 1Fh 20h General Purpose Register 96 Bytes 7Fh Bank 0
General Purpose Register(2) 96 Bytes
Note 1: 2:
Unimplemented data memory locations, read as `0'. Not a physical register. On the PIC16F914, unimplemented data memory locations, read as `0'.
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FIGURE 2-5: PIC16F946 SPECIAL FUNCTION REGISTERS
File Address Indirect addr. (1) 80h OPTION_REG 81h PCL 82h STATUS 83h FSR 84h TRISA 85h TRISB 86h TRISC 87h TRISD 88h TRISE 89h PCLATH 8Ah INTCON 8Bh PIE1 8Ch PIE2 8Dh PCON 8Eh OSCCON 8Fh OSCTUNE 90h ANSEL 91h PR2 92h SSPADD 93h SSPSTAT 94h WPUB 95h IOCB 96h CMCON1 97h TXSTA 98h SPBRG 99h 9Ah 9Bh CMCON0 9Ch VRCON 9Dh ADRESL 9Eh ADCON1 9Fh A0h General Purpose Register 80 Bytes accesses 70h-7Fh Bank 1 EFh F0h FFh File Address Indirect addr. (1) 100h TMR0 101h PCL 102h STATUS 103h FSR 104h WDTCON 105h PORTB 106h LCDCON 107h LCDPS 108h LVDCON 109h PCLATH 10Ah INTCON 10Bh EEDATL 10Ch EEADRL 10Dh EEDATH 10Eh EEADRH 10Fh LCDDATA0 110h LCDDATA1 111h LCDDATA2 112h LCDDATA3 113h LCDDATA4 114h LCDDATA5 115h LCDDATA6 116h LCDDATA7 117h LCDDATA8 118h LCDDATA9 119h LCDDATA10 11Ah LCDDATA11 11Bh LCDSE0 11Ch LCDSE1 11Dh LCDSE2 11Eh 11Fh 120h General Purpose Register 80 Bytes accesses 70h-7Fh Bank 2 16Fh 170h 17Fh File Address Indirect addr. (1) 180h OPTION_REG 181h PCL 182h STATUS 183h FSR 184h TRISF 185h TRISB 186h TRISG 187h PORTF 188h PORTG 189h PCLATH 18Ah INTCON 18Bh EECON1 18Ch (1) EECON2 18Dh Reserved 18Eh Reserved 18Fh LCDDATA12 190h LCDDATA13 191h LCDDATA14 192h LCDDATA15 193h LCDDATA16 194h LCDDATA17 195h LCDDATA18 196h LCDDATA19 197h LCDDATA20 198h LCDDATA21 199h LCDDATA22 19Ah LCDDATA23 19Bh LCDSE3 19Ch LCDSE4 19Dh LCDSE5 19Eh 19Fh 1A0h General Purpose Register 80 Bytes accesses 70h-7Fh Bank 3 1EFh 1F0h 1FFh File Address Indirect addr. (1) 00h TMR0 01h PCL 02h STATUS 03h FSR 04h PORTA 05h PORTB 06h PORTC 07h PORTD 08h PORTE 09h PCLATH 0Ah INTCON 0Bh PIR1 0Ch PIR2 0Dh TMR1L 0Eh TMR1H 0Fh T1CON 10h TMR2 11h T2CON 12h SSPBUF 13h SSPCON 14h CCPR1L 15h CCPR1H 16h CCP1CON 17h RCSTA 18h TXREG 19h RCREG 1Ah CCPR2L 1Bh CCPR2H 1Ch CCP2CON 1Dh ADRESH 1Eh ADCON0 1Fh 20h General Purpose Register 96 Bytes 7Fh Bank 0
Note 1:
Unimplemented data memory locations, read as `0'. Not a physical register.
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TABLE 2-1:
Addr Bank 0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh(2) 1Ch(2) 1Dh(2) 1Eh 1Fh INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(2) PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Program Counter's (PC) Least Significant Byte IRP RA7 RB7 RC7 RD7 RE7(3) -- GIE EEIF OSFIF RP1 RA6 RB6 RC6 RD6 RE6(3) -- PEIE ADIF C2IF RP0 RA5 RB5 RC5 RD5 RE5(3) -- T0IE RCIF C1IF TO RA4 RB4 RC4 RD4 RE4(3) INTE TXIF LCDIF PD RA3 RB3 RC3 RD3 RE3 RBIE SSPIF -- Z RA2 RB2 RC2 RD2 RE2(2) T0IF CCP1IF LVDIF DC RA1 RB1 RC1 RD1 RE1(2) INTF TMR2IF -- C RA0 RB0 RC0 RD0 RE0(2) RBIF TMR1IF CCP2IF(2) Indirect Data Memory Address Pointer xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ---0 0000 0000 000x 0000 0000 0000 -0-0 xxxx xxxx xxxx xxxx TMR1CS T2CKPS1 SSPM1 TMR1ON T2CKPS0 SSPM0 0000 0000 0000 0000 TOUTPS2 SSPEN TOUTPS1 CKP TOUTPS0 SSPM3 TMR2ON SSPM2 -000 0000 xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx CCP1M3 ADDEN CCP1M2 FERR CCP1M1 OERR CCP1M0 RX9D --00 0000 0000 000x 0000 0000 0000 0000 xxxx xxxx xxxx xxxx CCP2M3 CHS1 CCP2M2 CHS0 CCP2M1 GO/DONE CCP2M0 ADON --00 0000 xxxx xxxx CHS2 0000 0000 41,226 99,226 40,226 32,226 41,226 44,226 54,226 62,226 71,226 76,226 40,226 34,226 37,226 38,226 102,226 102,226 105,226 107,226 108,226 196,226 195,226 213,226 213,226 212,226 131,226 130,226 128,227 213,227 213,227 212,227 182,227 180,227 Name
PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page
Write Buffer for upper 5 bits of Program Counter
Holding Register for the Least Significant Byte of the 16-bit TMR1 Holding Register for the Most Significant Byte of the 16-bit TMR1 T1GINV -- WCOL TMR1GE TOUTPS3 SSPOV T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Timer2 Module Register Synchronous Serial Port Receive Buffer/Transmit Register Capture/Compare/PWM Register 1 (LSB) Capture/Compare/PWM Register 1 (MSB) -- SPEN -- RX9 CCP1X SREN CCP1Y CREN
USART Transmit Data Register USART Receive Data Register Capture/Compare/PWM Register 2 (LSB) Capture/Compare/PWM Register 2 (MSB) -- ADFM -- VCFG1 CCP2X VCFG0 CCP2Y A/D Result Register High Byte
Legend: Note 1: 2: 3:
- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. PIC16F914/917 and PIC16F946 only, forced `0' on PIC16F913/916. PIC16F946 only, forced to `0' on PIC16F91X.
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TABLE 2-2:
Addr Bank 1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh INDF OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD(3) TRISE PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE ANSEL PR2 SSPADD SSPSTAT WPUB IOCB CMCON1 TXSTA SPBRG -- -- CMCON0 VRCON ADRESL ADCON1 Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU IRP TRISA7 TRISB7 TRISC7 TRISD7 -- GIE EEIE OSFIE -- -- -- ANS7(3) INTEDG RP1 TRISA6 TRISB6 TRISC6 TRISD6 -- PEIE ADIE C2IE -- IRCF2 -- ANS6(3) T0CS RP0 TRISA5 TRISB5 TRISC5 TRISD5 -- T0IE RCIE C1IE -- IRCF1 -- ANS5(3) T0SE TO TRISA4 TRISB4 TRISC4 TRISD4 PSA PD TRISA3 TRISB3 TRISC3 TRISD3 PS2 Z TRISA2 TRISB2 TRISC2 TRISD2 PS1 DC TRISA1 TRISB1 TRISC1 TRISD1 PS0 C TRISA0 TRISB0 TRISC0 TRISD0 Program Counter's (PC) Least Significant Byte Indirect Data Memory Address Pointer xxxx xxxx 1111 1111 0000 0000 0001 1xxx xxxx xxxx 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---0 0000 0000 000x 0000 0000 0000 -0-0 ---1 --qq -110 q000 ---0 0000 1111 1111 1111 1111 0000 0000 R/W WPUB2 -- -- BRGH SPBRG2 UA WPUB1 -- T1GSS TRMT SPBRG1 BF WPUB0 -- C2SYNC TX9D SPBRG0 0000 0000 1111 1111 0000 ------- --10 0000 -010 0000 0000 -- -- C2INV VRR ADCS1 C1INV -- ADCS0 CIS VR3 -- CM2 VR2 -- CM1 VR1 -- CM0 VR0 -- 0000 0000 0-0- 0000 xxxx xxxx -000 ----- ADCS2 D/A WPUB5 IOCB5 -- TXEN SPBRG5 P WPUB4 IOCB4 -- SYNC SPBRG4 S WPUB3 -- -- -- SPBRG3 41,226 33,227 40,226 32,226 41,226 44,227 54,227 62,227 71,227 76,227 40,226 34,226 35,227 36,227 39,227 88,227 92,227 43,227 107,227 202,227 194,227 55,227 54,227 117,227 130,227 132,227 -- -- 116,227 118,227 182,227 181,227 Name
PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page
TRISE7(2) TRISE6(2) TRISE5(2) TRISE4(2) TRISE3(5) TRISE2(3) TRISE1(3) TRISE0(3) Write Buffer for the upper 5 bits of the Program Counter INTE TXIE LCDIE SBOREN IRCF0 TUN4 ANS4 RBIE SSPIE -- -- OSTS(4) TUN3 ANS3 T0IF CCP1IE LVDIE -- HTS TUN2 ANS2 INTF TMR2IE -- POR LTS TUN1 ANS1 RBIF TMR1IE CCP2IE(3) BOR SCS TUN0 ANS0
Timer2 Period Register Synchronous Serial Port (I2C mode) Address Register SMP WPUB7 IOCB7 -- CSRC SPBRG7 CKE WPUB6 IOCB6 -- TX9 SPBRG6
Unimplemented Unimplemented C2OUT VREN -- C1OUT
A/D Result Register Low Byte
Legend: Note 1: 2: 3: 4: 5:
- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. PIC16F946 only, forced `0' on PIC16F91X. PIC16F914/917 and PIC16F946 only, forced `0' on PIC16F913/916. The value of the OSTS bit is dependent on the value of the Configuration Word (CONFIG) of the device. See Section 4.2 "Oscillator Control". Bit is read-only; TRISE3 = 1 always.
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TABLE 2-3:
Addr Bank 2 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h INDF TMR0 PCL STATUS FSR WDTCON PORTB LCDCON LCDPS LVDCON Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Program Counter's (PC) Least Significant Byte IRP -- RB7 LCDEN WFT -- -- GIE EEDATL7 -- -- SEG7 COM0 SEG15 COM0 SEG23 COM0 SEG7 COM1 SEG15 COM1 SEG23 COM1 SEG7 COM2 SEG15 COM2 SEG23 COM2 SEG7 COM3 SEG15 COM3 SEG23 COM3 SE7 SE15 SE23 RP1 -- RB6 SLPEN BIASMD -- -- PEIE EEDATL6 -- -- SEG6 COM0 SEG14 COM0 SEG22 COM0 SEG6 COM1 SEG14 COM1 SEG22 COM1 SEG6 COM2 SEG14 COM2 SEG22 COM2 SEG6 COM3 SEG14 COM3 SEG22 COM3 SE6 SE14 SE22 RP0 -- RB5 WERR LCDA IRVST -- T0IE EEDATL5 TO WDTPS3 RB4 VLCDEN WA LVDEN INTE EEDATL4 PD WDTPS2 RB3 CS1 LP3 -- RBIE EEDATL3 EEADRL3 EEDATH3 SEG3 COM0 SEG11 COM0 SEG19 COM0 SEG3 COM1 SEG11 COM1 SEG19 COM1 SEG3 COM2 SEG11 COM2 SEG19 COM2 SEG3 COM3 SEG11 COM3 SEG19 COM3 SE3 SE11 SE19 Z WDTPS1 RB2 CS0 LP2 LVDL2 T0IF EEDATL2 EEADRL2 EEDATH2 SEG2 COM0 SEG10 COM0 SEG18 COM0 SEG2 COM1 SEG10 COM1 SEG18 COM1 SEG2 COM2 SEG10 COM2 SEG18 COM2 SEG2 COM3 SEG10 COM3 SEG18 COM3 SE2 SE10 SE18 DC WDTPS0 RB1 LMUX1 LP1 LVDL1 INTF EEDATL1 EEADRL1 EEDATH1 SEG1 COM0 SEG9 COM0 SEG17 COM0 SEG1 COM1 SEG9 COM1 SEG17 COM1 SEG1 COM2 SEG9 COM2 SEG17 COM2 SEG1 COM3 SEG9 COM3 SEG17 COM3 SE1 SE9 SE17 C SWDTEN RB0 LMUX0 LP0 LVDL0 RBIF EEDATL0 Indirect Data Memory Address Pointer xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx ---0 1000 xxxx xxxx 0001 0011 0000 0000 --00 -100 ---0 0000 0000 000x 0000 0000 41,226 99,226 40,226 32,226 41,226 235,227 54,226 145,227 146,227 145,228 40,226 34,226 188,228 188,228 188,228 188,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 -- Name
PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page
10Ah PCLATH 10Bh INTCON 10Ch EEDATL 10Dh EEADRL 10Eh EEDATH 10Fh EEADRH 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh LCDDATA0 LCDDATA1 LCDDATA2(2) LCDDATA3 LCDDATA4 LCDDATA5(2) LCDDATA6 LCDDATA7 LCDDATA8(2) LCDDATA9 LCDDATA10 LCDDATA11(2)
Write Buffer for the upper 5 bits of the Program Counter
EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEDATH5 EEDATH4 -- SEG5 COM0 SEG13 COM0 SEG21 COM0 SEG5 COM1 SEG13 COM1 SEG21 COM1 SEG5 COM2 SEG13 COM2 SEG21 COM2 SEG5 COM3 SEG13 COM3 SEG21 COM3 SE5 SE13 SE21 SEG4 COM0 SEG12 COM0 SEG20 COM0 SEG4 COM1 SEG12 COM1 SEG20 COM1 SEG4 COM2 SEG12 COM2 SEG20 COM2 SEG4 COM3 SEG12 COM3 SEG20 COM3 SE4 SE12 SE20
EEADRL0 0000 0000 EEDATH0 --00 0000 SEG0 COM0 SEG8 COM0 SEG16 COM0 SEG0 COM1 SEG8 COM1 SEG16 COM1 SEG0 COM2 SEG8 COM2 SEG16 COM2 SEG0 COM3 SEG8 COM3 SEG16 COM3 SE0 SE8 SE16
EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---0 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 --
11Ch LCDSE0(3) 11Dh LCDSE1(3) 11Eh 11Fh Legend: Note 1: 2: 3: LCDSE2(2,3) --
Unimplemented
- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. PIC16F914/917 and PIC16F946 only. This register is only initialized by a POR or BOR reset and is unchanged by other Resets.
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TABLE 2-4:
Addr Bank 3 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh Legend: Note 1: 2: 3: Addressing this location uses contents of FSR to address data memory (not a physical register) OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 PCL STATUS FSR TRISF(3) TRISB TRISG(3) PORTF(3) PORTG(3) PCLATH INTCON EECON1 EECON2 -- -- LCDDATA12(3) LCDDATA13(3) LCDDATA14(3) LCDDATA15(3) LCDDATA16(3) LCDDATA17(3) LCDDATA18(3) LCDDATA19(3) LCDDATA20(3) LCDDATA21(3) LCDDATA22(3) LCDDATA23(3) LCDSE3(2, 3) LCDSE4 --
(2, 3)
PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page
Name
INDF
xxxx xxxx 1111 1111 0000 0000
41,226 33,227 40,226 32,226 41,226 81,228 54,227 84,228 81,228 84,228 40,226 34,226 189,229 187 -- -- 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,229 147,229 147,229 --
Program Counter (PC) Least Significant Byte IRP TRISF7 TRISB7 -- RF7 -- -- GIE EEPGD Reserved Reserved SEG31 COM0 SEG39 COM0 -- SEG31 COM1 SEG39 COM1 -- SEG31 COM2 SEG39 COM2 -- SEG31 COM3 SEG39 COM3 -- SE31 SE39 -- SEG30 COM0 SEG38 COM0 -- SEG30 COM1 SEG38 COM1 -- SEG30 COM2 SEG38 COM2 -- SEG30 COM3 SEG38 COM3 -- SE30 SE38 -- SEG29 COM0 SEG37 COM0 -- SEG29 COM1 SEG37 COM1 -- SEG29 COM2 SEG37 COM2 -- SEG29 COM3 SEG37 COM3 -- SE29 SE37 -- SEG28 COM0 SEG36 COM0 -- SEG28 COM1 SEG36 COM1 -- SEG28 COM2 SEG36 COM2 -- SEG28 COM3 SEG36 COM3 -- SE28 SE36 -- SEG27 COM0 SEG35 COM0 -- SEG27 COM1 SEG35 COM1 -- SEG27 COM2 SEG35 COM2 -- SEG27 COM3 SEG35 COM3 -- SE27 SE35 -- SEG26 COM0 SEG34 COM0 -- SEG26 COM1 SEG34 COM1 -- SEG26 COM2 SEG34 COM2 -- SEG26 COM3 SEG34 COM3 -- SE26 SE34 -- SEG25 COM0 SE33 COM0 SEG41 COM0 SEG25 COM1 SEG33 COM1 SEG41 COM1 SEG25 COM2 SEG33 COM2 SEG41 COM2 SEG25 COM3 SEG33 COM3 SEG41 COM3 SE25 SE33 SE41 SEG24 COM0 SEG32 COM0 SEG40 COM0 SEG24 COM1 SEG32 COM1 SEG40 COM1 SEG24 COM2 SEG32 COM2 SEG40 COM2 SEG24 COM3 SEG32 COM3 SEG40 COM3 SE24 SE32 SE40 RP1 TRISF6 TRISB6 -- RF6 -- -- PEIE -- RP0 TRISF5 TRISB5 TRISG5 RF5 RG5 -- T0IE -- TO TRISF4 TRISB4 TRISG4 RF4 RG4 INTE -- PD TRISF3 TRISB3 TRISG3 RF3 RG3 RBIE WRERR Z TRISF2 TRISB2 TRISG2 RF2 RG2 T0IF WREN DC TRISF1 TRISB1 TRISG1 RF1 RG1 INTF WR C TRISF0 TRISB0 TRISG0 RF0 RG0 RBIF RD Indirect Data Memory Address Pointer
0001 1xxx xxxx xxxx 1111 1111 1111 1111 --11 1111 xxxx xxxx --xx xxxx ---0 0000 0000 000x 0--- x000 ---- ----- -- xxxx xxxx xxxx xxxx ---- --xx xxxx xxxx xxxx xxxx ---- --xx xxxx xxxx xxxx xxxx ---- --xx xxxx xxxx xxxx xxxx ---- --xx 0000 0000 0000 0000 ---- --00 --
Write Buffer for the upper 5 bits of the Program Counter
EEPROM Control Register 2 (not a physical register)
LCDSE5(2, 3)
Unimplemented
- = Unimplemented locations read as `0', u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. This register is only initialized by a POR or BOR reset and is unchanged by other Resets. PIC16F946 only.
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2.2.2.1 STATUS Register
The STATUS register, shown in Register 2-1, contains: * the arithmetic status of the ALU * the Reset status * the bank select bits for data memory (SRAM) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as `000u u1uu' (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (see Section 17.0 "Instruction Set Summary"). Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction.
REGISTER 2-1:
R/W-0 IRP bit 7 Legend: R = Readable bit -n = Value at POR bit 7
STATUS: STATUS REGISTER
R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC(1) R/W-x C(1) bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h-1FFh) 0 = Bank 0, 1 (00h-FFh) RP<1:0>: Register Bank Select bits (used for direct addressing) 00 = Bank 0 (00h-7Fh) 01 = Bank 1 (80h-FFh) 10 = Bank 2 (100h-17Fh) 11 = Bank 3 (180h-1FFh) TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred For Borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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2.2.2.2 OPTION register
Note: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit of the OPTION register to `1'. See Section 6.3 "Timer1 Prescaler". The OPTION register, shown in Register 2-2, is a readable and writable register, which contains various control bits to configure: * * * * Timer0/WDT prescaler External RB0/INT interrupt Timer0 Weak pull-ups on PORTB
REGISTER 2-2:
R/W-1 RBPU bit 7 Legend: R = Readable bit -n = Value at POR bit 7
OPTION_REG: OPTION REGISTER
R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual bits in the WPUB register INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: Timer0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 Timer0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
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2.2.2.3 INTCON Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTB change and external RB0/INT/SEG0 pin interrupts.
REGISTER 2-3:
R/W-0 GIE bit 7 Legend: R = Readable bit -n = Value at POR bit 7
INTCON: INTERRUPT CONTROL REGISTER
R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 RBIE(1) R/W-0 T0IF
(2)
R/W-0 INTF
R/W-x RBIF bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: PORTB Change Interrupt Enable bit(1) 1 = Enables the PORTB change interrupt 0 = Disables the PORTB change interrupt T0IF: Timer0 Overflow Interrupt Flag bit(2) 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: PORTB Change Interrupt Flag bit 1 = When at least one of the PORTB general purpose I/O pins changed state (must be cleared in software) 0 = None of the PORTB general purpose I/O pins have changed state The appropriate bits in the IOCB register must also be set. T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing T0IF bit.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: 2:
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2.2.2.4 PIE1 Register
Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. The PIE1 register contains the interrupt enable bits, as shown in Register 2-4.
REGISTER 2-4:
R/W-0 EEIE bit 7 Legend: R = Readable bit -n = Value at POR bit 7
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0 ADIE R/W-0 RCIE R/W-0 TXIE R/W-0 SSPIE R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt ADIE: A/D Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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2.2.2.5 PIE2 Register
Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. The PIE2 register contains the interrupt enable bits, as shown in Register 2-5.
REGISTER 2-5:
R/W-0 OSFIE bit 7 Legend: R = Readable bit -n = Value at POR bit 7
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0 C2IE R/W-0 C1IE R/W-0 LCDIE U-0 -- R/W-0 LVDIE U-0 -- R/W-0 CCP2IE(1) bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables oscillator fail interrupt 0 = Disables oscillator fail interrupt C2IE: Comparator C2 Interrupt Enable bit 1 = Enables Comparator C2 interrupt 0 = Disables Comparator C2 interrupt C1IE: Comparator C1 Interrupt Enable bit 1 = Enables Comparator C1 interrupt 0 = Disables Comparator C1 interrupt LCDIE: LCD Module Interrupt Enable bit 1 = Enables LCD interrupt 0 = Disables LCD interrupt Unimplemented: Read as `0' LVDIE: Low Voltage Detect Interrupt Enable bit 1 = Enables LVD Interrupt 0 = Disables LVD Interrupt Unimplemented: Read as `0' CCP2IE: CCP2 Interrupt Enable bit(1) 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt PIC16F914/PIC16F917/PIC16F946 only.
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1 bit 0
Note 1:
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2.2.2.6 PIR1 Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR1 register contains the interrupt flag bits, as shown in Register 2-6.
REGISTER 2-6:
R/W-0 EEIF bit 7 Legend: R = Readable bit -n = Value at POR bit 7
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0 ADIF R-0 RCIF R-0 TXIF R/W-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
EEIF: EE Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not started ADIF: A/D Converter Interrupt Flag bit 1 = A/D conversion complete (must be cleared in software) 0 = A/D conversion has not completed or has not been started RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full (cleared by reading RCREG) 0 = The USART receive buffer is not full TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty (cleared by writing to TXREG) 0 = The USART transmit buffer is full SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit 1 = The Transmission/Reception is complete (must be cleared in software) 0 = Waiting to Transmit/Receive CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode Unused in this mode TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = A Timer2 to PR2 match occurred (must be cleared in software) 0 = No Timer2 to PR2 match occurred TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = The TMR1 register overflowed (must be cleared in software) 0 = The TMR1 register did not overflow
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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2.2.2.7 PIR2 Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR2 register contains the interrupt flag bits, as shown in Register 2-7.
REGISTER 2-7:
R/W-0 OSFIF bit 7 Legend: R = Readable bit -n = Value at POR bit 7
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0 C2IF R/W-0 C1IF R/W-0 LCDIF U-0 -- R/W-0 LVDIF U-0 -- R/W-0 CCP2IF(1) bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
OSFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = System clock operating C2IF: Comparator C2 Interrupt Flag bit 1 = Comparator output (C2OUT bit) has changed (must be cleared in software) 0 = Comparator output (C2OUT bit) has not changed C1IF: Comparator C1 Interrupt Flag bit 1 = Comparator output (C1OUT bit) has changed (must be cleared in software) 0 = Comparator output (C1OUT bit) has not changed LCDIF: LCD Module Interrupt bit 1 = LCD has generated an interrupt 0 = LCD has not generated an interrupt Unimplemented: Read as `0' LVDIF: Low Voltage Detect Interrupt Flag bit 1 = LVD has generated an interrupt 0 = LVD has not generated an interrupt Unimplemented: Read as `0' CCP2IF: CCP2 Interrupt Flag bit(1) Capture Mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode PIC16F914/PIC16F917/PIC16F946 only.
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1 bit 0
Note 1:
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2.2.2.8 PCON Register
The Power Control (PCON) register contains flag bits (see Table 16-2) to differentiate between a: * * * * Power-on Reset (POR) Brown-out Reset (BOR) Watchdog Timer Reset (WDT) External MCLR Reset
The PCON register also controls the software enable of the BOR. The PCON register bits are shown in Register 2-8.
REGISTER 2-8:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4
PCON: POWER CONTROL REGISTER
U-0 -- U-0 -- R/W-1 SBOREN U-0 -- U-0 -- R/W-0 POR R/W-x BOR bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' SBOREN: Software BOR Enable bit(1) 1 = BOR enabled 0 = BOR disabled Unimplemented: Read as `0' POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) Set BOREN<1:0> = 01 in the Configuration Word register for this bit to control the BOR.
bit 3-2 bit 1
bit 0
Note 1:
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2.3 PCL and PCLATH
Note 1: There are no Status bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-6 shows the two situations for the loading of the PC. The upper example in Figure 2-6 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in Figure 2-6 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH).
2.4
Program Memory Paging
FIGURE 2-6:
PCH 12 PC 5 8 7
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 0 Instruction with PCL as Destination ALU Result
PCLATH<4:0>
8
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 11 10 8 7 PCL 0 GOTO, CALL OPCODE<10:0>
All PIC16F91X/946 devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction, the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is POPed off the stack. Therefore, manipulation of the PCLATH<4:3> bits is not required for the RETURN instructions (which POPs the address from the stack). Note: The contents of the PCLATH register are unchanged after a RETURN or RETFIE instruction is executed. The user must rewrite the contents of the PCLATH register for any subsequent subroutine calls or GOTO instructions.
PCLATH
2.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, "Implementing a Table Read" (DS00556).
Example 2-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that PCLATH is saved and restored by the Interrupt Service Routine (if interrupts are used).
EXAMPLE 2-1:
CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0
2.3.2
STACK
ORG 500h BCF PCLATH,4 BSF PCLATH,3 CALL SUB1_P1 : : ORG 900h SUB1_P1 : : RETURN
The PIC16F91X/946 family has an 8-level x 13-bit wide hardware stack (see Figures 2-1 and 2-2). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth PUSH overwrites the value that was stored from the first PUSH. The tenth PUSH overwrites the second PUSH (and so on).
;Select page 1 ;(800h-FFFh) ;Call subroutine in ;page 1 (800h-FFFh) ;page 1 (800h-FFFh) ;called subroutine ;page 1 (800h-FFFh) ;return to ;Call subroutine ;in page 0 ;(000h-7FFh)
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2.5 Indirect Addressing, INDF and FSR Registers
EXAMPLE 2-2:
MOVLW MOVWF BANKISEL NEXT CLRF INCF BTFSS GOTO CONTINUE
INDIRECT ADDRESSING
020h FSR 020h INDF FSR FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit of the STATUS register, as shown in Figure 2-7. A simple program to clear RAM location 020h-02Fh using indirect addressing is shown in Example 2-2.
FIGURE 2-7:
DIRECT/INDIRECT ADDRESSING PIC16F91X/946
Indirect Addressing 0 IRP 7 File Select Register 0
Direct Addressing RP1 RP0 6 From Opcode
Bank Select
Location Select 00 00h 01 10 11
Bank Select 180h
Location Select
Data Memory
7Fh Bank 0 Note: Bank 1 Bank 2 Bank 3
1FFh
For memory map detail, see Figures 2-3 and 2-4.
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3.0 I/O PORTS
3.1 ANSEL Register
The PIC16F913/914/916/917/946 family of devices includes several 8-bit PORT registers along with their corresponding TRIS registers and one four bit port: * * * * * * * PORTA and TRISA PORTB and TRISB PORTC and TRISC PORTD and TRISD(1) PORTE and TRISE PORTF and TRISF(2) PORTG and TRISG(2) Note 1: PIC16F914/917 and PIC16F946 only. 2: PIC16F946 only PORTA, PORTB, PORTC and RE3/MCLR/VPP are implemented on all devices. PORTD and RE<2:0> (PORTE) are implemented only on the PIC16F914/917 and PIC16F946. RE<7:4> (PORTE), PORTF and PORTG are implemented only on the PIC16F946. The ANSEL register (Register 3-1) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSEL bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSEL bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port.
REGISTER 3-1:
R/W-1 ANS7(2) bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
ANSEL: ANALOG SELECT REGISTER
R/W-1 ANS6(2) R/W-1 ANS5(2) R/W-1 ANS4 R/W-1 ANS3 R/W-1 ANS2 R/W-1 ANS1 R/W-1 ANS0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ANS<7:0>: Analog Select bits Analog select between analog or digital function on pins AN<7:0>, respectively. 1 = Analog input. Pin is assigned as analog input(1). 0 = Digital I/O. Pin is assigned to port or special function. Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. PIC16F914/PIC16F917/PIC16F946 only.
Note 1:
2:
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3.2 PORTA and TRISA Registers
PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 3-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Example 3-1 shows how to initialize PORTA. Five of the pins of PORTA can be configured as analog inputs. These pins, RA5 and RA<3:0>, are configured as analog inputs on device power-up and must be reconfigured by the user to be used as I/O's. This is done by writing the appropriate values to the CMCON0 and ANSEL registers (see Example 3-1). Reading the PORTA register (Register 3-2) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port means that the port pins are read, this value is modified and then written to the PORT data latch. The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read `0'. Note 1: The CMCON0 and ANSEL registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
EXAMPLE 3-1:
BANKSEL CLRF BANKSEL MOVLW MOVWF CLRF MOVLW MOVWF PORTA PORTA TRISA 07h CMCON0 ANSEL 0F0h TRISA
INITIALIZING PORTA
; ;Init PORTA ; ;Set RA<2:0> to ;digital I/O ;Make all PORTA digital I/O ;Set RA<7:4> as inputs ;and set RA<3:0> as outputs
REGISTER 3-2:
R/W-x RA7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
PORTA: PORTA REGISTER
R/W-x RA6 R/W-x RA5 R/W-x RA4 R/W-x RA3 R/W-x RA2 R/W-x RA1 R/W-x RA0 bit 0
W = Writable bit `1' = Bit is set RA<7:0>: PORTA I/O Pin bits 1 = Port pin is >VIH min. 0 = Port pin is U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
REGISTER 3-3:
R/W-1 TRISA7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
TRISA: PORTA TRI-STATE REGISTER
R/W-1 TRISA6 R/W-1 TRISA5 R/W-1 TRISA4 R/W-1 TRISA3 R/W-1 TRISA2 R/W-1 TRISA1 R/W-1 TRISA0 bit 0
W = Writable bit `1' = Bit is set TRISA<7:0>: PORTA Tri-State Control bits 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Note
1:
TRISA<7:6> always reads `1' in XT, HS and LP Oscillator modes.
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3.2.1 PIN DESCRIPTIONS AND DIAGRAMS
Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions, refer to the appropriate section in this data sheet.
3.2.1.1
RA0/AN0/C1-/SEG12
Figure 3-1 shows the diagram for this pin. The RA0 pin is configurable to function as one of the following: * * * * a general purpose I/O an analog input for the ADC an analog input for Comparator C1 an analog output for the LCD
FIGURE 3-1:
BLOCK DIAGRAM OF RA0
Data Bus D CK Q Q VDD
WR PORTA
Data Latch D WR TRISA CK Q Q VSS Analog Input or SE12 and LCDEN RD TRISA SE12 and LCDEN TTL Input Buffer I/O Pin
TRIS Latch
RD PORTA SEG12 SE12 and LCDEN To A/D Converter and Comparator
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3.2.1.2 RA1/AN1/C2-/SEG7
Figure 3-2 shows the diagram for this pin. The RA1 pin is configurable to function as one of the following: * * * * a general purpose I/O an analog input for the ADC an analog input for Comparator C2 an analog output for the LCD
FIGURE 3-2:
BLOCK DIAGRAM OF RA1
Data Bus D CK Q Q VDD
WR PORTA
Data Latch D WR TRISA CK Q Q VSS Analog Input or SE7 and LCDEN RD TRISA SE7 and LCDEN TTL Input Buffer I/O Pin
TRIS Latch
RD PORTA SEG7 SE7 and LCDEN To A/D Converter and Comparator
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3.2.1.3 RA2/AN2/C2+/VREF-/COM2
Figure 3-3 shows the diagram for this pin. The RA2 pin is configurable to function as one of the following: * * * * * a general purpose I/O an analog input for the ADC an analog input for Comparator C2 a voltage reference input for the ADC an analog output for the LCD
FIGURE 3-3:
BLOCK DIAGRAM OF RA2
Data Bus D CK Q Q VDD
WR PORTA
Data Latch D WR TRISA CK Q Q VSS Analog Input or LCDEN and LMUX<1:0> = 1X LCDEN and LMUX<1:0> = 1X TTL Input Buffer I/O Pin
TRIS Latch
RD TRISA
RD PORTA LCDEN and LMUX<1:0> = 1X
COM2
To A/D Converter and Comparator To A/D Module VREF- Input
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3.2.1.4 RA3/AN3/C1+/VREF+/COM3/SEG15
Figure 3-4 shows the diagram for this pin. The RA3 pin is configurable to function as one of the following: * * * * * a general purpose input an analog input for the ADC an analog input from Comparator C1 a voltage reference input for the ADC analog outputs for the LCD
FIGURE 3-4:
BLOCK DIAGRAM OF RA3
Data Bus WR PORTA
D CK
Q Q VDD
Data Latch D WR TRISA CK Q Q VSS Analog Input or LCDMODE_EN(2) RD TRISA TTL Input Buffer I/O Pin
TRIS Latch
LCDMODE_EN(2)
RD PORTA COM3(1) or SEG15 LCDMODE_EN(2)
To A/D Converter and Comparator To A/D Module VREF+ Input
Note 1: 2:
PIC16F913/916 only. For the PIC16F913/916, the LCDMODE_EN = LCDEN and (SE15 or LMUX<1:0> = 11). For the PIC16F914/917 and PIC16F946, the LCDMODE_EN = LCDEN and SE15.
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3.2.1.5 RA4/C1OUT/T0CKI/SEG4
Figure 3-5 shows the diagram for this pin. The RA4 pin is configurable to function as one of the following: * * * * a general purpose I/O a digital output from Comparator C1 a clock input for Timer0 an analog output for the LCD
FIGURE 3-5:
BLOCK DIAGRAM OF RA4
CM<2:0> = 110 or 101 C1OUT Data Bus WR PORTA D CK D WR TRISA CK Q Q Q VSS Q SE4 and LCDEN TTL Input Buffer TRIS Latch I/O Pin 1 0 VDD Data Latch
RD TRISA
SE4 and LCDEN
RD PORTA Schmitt Trigger T0CKI SE4 and LCDEN SE4 and LCDEN
SEG4
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3.2.1.6 RA5/AN4/C2OUT/SS/SEG5
Figure 3-6 shows the diagram for this pin. The RA5 pin is configurable to function as one of the following: * * * * * a general purpose I/O a digital output from Comparator C2 a slave select input an analog output for the LCD an analog input for the ADC
FIGURE 3-6:
BLOCK DIAGRAM OF RA5
CM<2:0> = 110 or 101 C2OUT Data Bus D CK D WR TRISA CK Q Q Q VSS Q Analog Input or SE5 and LCDEN SE5 and LCDEN TTL Input Buffer TRIS Latch I/O Pin 1 0 VDD Data Latch
WR PORTA
RD TRISA
RD PORTA To SS Input SE5 and LCDEN SEG5 To A/D Converter
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3.2.1.7 RA6/OSC2/CLKOUT/T1OSO
Figure 3-7 shows the diagram for this pin. The RA6 pin is configurable to function as one of the following: * * * * a general purpose I/O a crystal/resonator connection a clock output a Timer1 oscillator connection
FIGURE 3-7:
BLOCK DIAGRAM OF RA6
FOSC = 1x1 CLKOUT (FOSC/4) 1 0 VDD
From OSC1 Oscillator Circuit
Data Bus WR PORTA
D CK D
Q Q Q
Data Latch I/O Pin VSS CK Q TRIS Latch FOSC = 00x, 010 or T1OSCEN TTL Input Buffer RD TRISA
WR TRISA FOSC = 00x, 010 or T1OSCEN
RD PORTA
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3.2.1.8 RA7/OSC1/CLKIN/T1OSI
Figure 3-8 shows the diagram for this pin. The RA7 pin is configurable to function as one of the following: * * * * a general purpose I/O a crystal/resonator connection a clock input a Timer1 oscillator connection
FIGURE 3-8:
BLOCK DIAGRAM OF RA7
To OSC2 Oscillator Circuit
FOSC = 011
Data Bus WR PORTA
D CK
Q Q
Data Latch D WR TRISA FOSC = 10x CK Q Q
VDD
I/O Pin VSS FOSC = 10x TTL Input Buffer
TRIS Latch
RD TRISA
RD PORTA
TABLE 3-1:
Name ADCON0 ANSEL CMCON0 CONFIG(1) OPTION_REG LCDCON LCDSE0 LCDSE1 PORTA SSPCON T1CON TRISA Legend: Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 ADFM ANS7 C2OUT CPD RBPU LCDEN SE7 SE15 RA7 WCOL T1GINV TRISA7 Bit 6 VCFG1 ANS6 C1OUT CP INTEDG SLPEN SE6 SE14 RA6 SSPOV TMR1GE TRISA6 Bit 5 VCFG0 ANS5 C2INV MCLRE T0CS WERR SE5 SE13 RA5 SSPEN TRISA5 Bit 4 CHS2 ANS4 C1INV PWRTE T0SE VLCDEN SE4 SE12 RA4 CKP TRISA4 Bit 3 CHS1 ANS3 CIS WDTE PSA CS1 SE3 SE11 RA3 SSPM3 TRISA3 Bit 2 CHS0 ANS2 CM2 FOSC2 PS2 CS0 SE2 SE10 RA2 SSPM2 T1SYNC TRISA2 Bit 1 GO/DONE ANS1 CM1 FOSC1 PS1 LMUX1 SE1 SE9 RA1 SSPM1 TMR1CS TRISA1 Bit 0 ADON ANS0 CM0 FOSC0 PS0 LMUX0 SE0 SE8 RA0 SSPM0 TMR1ON TRISA0 Value on POR, BOR 0000 0000 1111 1111 0000 0000 -- 1111 1111 0001 0011 0000 0000 0000 0000 xxxx xxxx 0000 0000 0000 0000 1111 1111 Value on all other Resets 0000 0000 1111 1111 0000 0000 -- 1111 1111 0001 0011 uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 1111 1111
T1CKPS1 T1CKPS0 T1OSCEN
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTA. See Configuration Word register (CONFIG) for operation of all register bits.
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3.3 PORTB and TRISB Registers 3.4 Additional PORTB Pin Functions
PORTB is an 8-bit bidirectional I/O port. All PORTB pins can have a weak pull-up feature, and PORTB<7:4> implements an interrupt-on-input change function. PORTB is also used for the Serial Flash programming interface and ICD interface. RB<7:6> are used as data and clock signals, respectively, for both serial programming and the in-circuit debugger features on the device. Also, RB0 can be configured as an external interrupt input.
3.4.1
WEAK PULL-UPS
EXAMPLE 3-2:
BANKSEL CLRF BANKSEL MOVLW MOVWF PORTB PORTB TRISB 0FFh TRISB
INITIALIZING PORTB
; ;Init PORTB ; ;Set RB<7:0> as inputs ;
Each of the PORTB pins has an individually configurable internal weak pull-up. Control bits WPUB<7:0> enable or disable each pull-up. Refer to Register 3-7. Each weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset by the RBPU bit of the OPTION register.
3.4.2
INTERRUPT-ON-CHANGE
Four of the PORTB pins are individually configurable as an interrupt-on-change pin. Control bits IOCB<7:4> enable or disable the interrupt function for each pin. Refer to Register 3-6. The interrupt-on-change feature is disabled on a Power-on Reset. For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of PORTB. The `mismatch' outputs of the last read are OR'd together to set the PORTB Change Interrupt flag bit (RBIF) in the INTCON register (Register 2-3). This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the interrupt by: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear the flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF. Reading or writing PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The latch holding the last read value is not affected by a MCLR nor Brown-out Reset. After these Resets, the RBIF flag will continue to be set if a mismatch is present. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not get set. Furthermore, since a read or write on a port affects all bits of that port, care must be taken when using multiple pins in Interrupt-on-change mode. Changes on one pin may not be seen while servicing changes on another pin.
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REGISTER 3-4:
R/W-x RB7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PORTB: PORTB REGISTER
R/W-x RB6 R/W-x RB5 R/W-x RB4 R/W-x RB3 R/W-x RB2 R/W-x RB1 R/W-x RB0 bit 0
RB<7:0>: PORTB I/O Pin bits 1 = Port pin is >VIH min. 0 = Port pin is REGISTER 3-5:
R/W-1 TRISB7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
TRISB: PORTB TRI-STATE REGISTER
R/W-1 TRISB6 R/W-1 TRISB5 R/W-1 TRISB4 R/W-1 TRISB3 R/W-1 TRISB2 R/W-1 TRISB1 R/W-1 TRISB0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TRISB<7:0>: PORTB Tri-State Control bits 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output
REGISTER 3-6:
R/W-0 IOCB7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-4
IOCB: PORTB INTERRUPT-ON-CHANGE REGISTER
R/W-0 IOCB6 R/W-0 IOCB5 R/W-0 IOCB4 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
IOCB<7:4>: Interrupt-on-Change bits 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled Unimplemented: Read as `0'
bit 3-0
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REGISTER 3-7:
R/W-1 WPUB7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
WPUB: WEAK PULL-UP REGISTER
R/W-1 WPUB6 R/W-1 WPUB5 R/W-1 WPUB4 R/W-1 WPUB3 R/W-1 WPUB2 R/W-1 WPUB1 R/W-1 WPUB0 bit 0
WPUB<7:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Global RBPU must be enabled for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in Output mode (TRISx<7:0> = 0).
Note 1: 2:
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3.4.3 PIN DESCRIPTIONS AND DIAGRAMS 3.4.3.2 RB1/SEG1
Each PORTB pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the LCD or interrupts, refer to the appropriate section in this data sheet. Figure 3-9 shows the diagram for this pin. The RB1 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
3.4.3.3
RB2/SEG2
3.4.3.1
RB0/INT/SEG0
Figure 3-9 shows the diagram for this pin. The RB0 pin is configurable to function as one of the following: * a general purpose I/O * an external edge triggered interrupt * an analog output for the LCD
Figure 3-9 shows the diagram for this pin. The RB2 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
3.4.3.4
RB3/SEG3
Figure 3-9 shows the diagram for this pin. The RB3 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
FIGURE 3-9:
BLOCK DIAGRAM OF RB<3:0>
WPUB<3:0> SE<3:0> VDD VDD P Weak Pull-up D CK Data Latch D Q Q I/O Pin VSS
RBPU Data Bus WR PORTB
WR TRISB
CK TRIS Latch SE<3:0> and LCDEN TTL Input Buffer
RD TRISB
RD PORTB SEG<3:0> SE<3:0> and LCDEN
Schmitt Trigger INT(1) SE0 and LCDEN
Note 1:
RB0 only.
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3.4.3.5 RB4/COM0
Figure 3-10 shows the diagram for this pin. The RB4 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
FIGURE 3-10:
BLOCK DIAGRAM OF RB4
WPUB<4> RBPU Data Bus WR PORTB D CK Data Latch D WR TRISB CK TRIS Latch RD TRISB LCDEN Q Q
LCDEN
VDD VDD P Weak Pull-up
I/O Pin VSS
TTL Input Buffer
RD PORTB D WR IOC CK Q Q
Q
D EN Q1
RD IOC Interrupt-onChange Set RBIF Q S R Write `0' to RBIF LCDEN From other RB<7:4> pins LCDEN Q
D EN RD PORTB
COM0
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3.4.3.6 RB5/COM1
Figure 3-11 shows the diagram for this pin. The RB5 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
FIGURE 3-11:
BLOCK DIAGRAM OF RB5
WPUB<5> RBPU Data Bus WR PORTB D CK Data Latch D WR TRISB CK TRIS Latch RD TRISB LCDEN and LMUX<1:0> Q Q I/O Pin VSS LCDEN and LMUX<1:0>
00
VDD VDD P Weak Pull-up
00
TTL Input Buffer
RD PORTB D WR IOC CK Q Q LCDEN and LMUX<1:0>
Q
D EN Q1
RD IOC Interrupt-onChange Set RBIF Q S R Write `0' to RBIF From other RB<7:4> pins
00
Q
D EN RD PORTB
COM1
LCDEN and LMUX<1:0>
00
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3.4.3.7 RB6/ICSPCLK/ICDCK/SEG14
Figure 3-12 shows the diagram for this pin. The RB6 pin is configurable to function as one of the following: * * * * a general purpose I/O an In-Circuit Serial ProgrammingTM clock an ICD clock input an analog output for the LCD
FIGURE 3-12:
BLOCK DIAGRAM OF RB6
Program Mode/ICD Mode WPUB<6> RBPU SE14 and LCDEN Data Bus WR PORTB D CK Data Latch D WR TRISB CK TRIS Latch RD TRISB RD PORTB D WR IOC CK Q Q Q SE14 and LCDEN TTL Input Buffer Q I/O Pin VSS VDD Weak P Pull-up VDD
Q
D EN Q1
RD IOC Set RBIF Interrupt-onChange Q S R Write `0' to RBIF Schmitt Trigger ICSPCLK From other RB<7:4> pins Program Mode/ICD Q
D EN RD PORTB
Program Mode or ICD Mode or (SE14 and LCDEN)
SEG14
SE14 and LCDEN
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3.4.3.8 RB7/ICSPDAT/ICDDAT/SEG13
Figure 3-13 shows the diagram for this pin. The RB7 pin is configurable to function as one of the following: * * * * a general purpose I/O an In-Circuit Serial ProgrammingTM I/O an ICD data I/O an analog output for the LCD
FIGURE 3-13:
BLOCK DIAGRAM OF RB7
PORT/Program Mode/ICD ICSPDAT
RBPU SE13 and LCDEN
VDD P Weak Pull-up 1 0 I/O Pin VSS VDD
Data Bus WR PORTB
D
Q
CK Data Latch D Q
WR TRISB PGD DRVEN
CK TRIS Latch 0 1 SE13 and LCDEN TTL Input Buffer
RD TRISB RD PORTB D WR IOC CK Q Q
Q
D EN Q1
RD IOC Program Mode/ICD
Interrupt-onChange
Set RBIF Q S R From other RB<7:4> pins
Q
D EN RD PORTB
Write `0' to RBIF Schmitt Trigger ICSPDAT/ICDDAT Program Mode or ICD Mode or (SE13 and LCDEN)
SEG13
SE13 and LCDEN
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TABLE 3-2:
Name INTCON IOCB LCDCON LCDSE0 LCDSE1 OPTION_REG PORTB TRISB WPUB Legend: Note 1: 2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7 GIE IOCB7 LCDEN SE7 SE15 RBPU RB7 TRISB7 WPUB7 Bit 6 PEIE IOCB6 SLPEN SE6 SE14 INTEDG RB6 TRISB6 WPUB6 Bit 5 T0IE IOCB5 WERR SE5 SE13 T0CS RB5 TRISB5 WPUB5 Bit 4 INTE IOCB4 VLCDEN SE4 SE12 T0SE RB4 TRISB4 WPUB4 Bit 3 RBIE -- CS1 SE3 SE11 PSA RB3 TRISB3 WPUB3 Bit 2 T0IF -- CS0 SE2 SE10 PS2 RB2 TRISB2 WPUB2 Bit 1 INTF -- LMUX1 SE1 SE9 PS1 RB1 TRISB1 WPUB1 Bit 0 RBIF -- LMUX0 SE0 SE8 PS0 RB0 TRISB0 WPUB0 Value on POR, BOR 0000 000x 0000 ---0001 0011 0000 0000 0000 0000 1111 1111 xxxx xxxx 1111 1111 1111 1111 Value on all other Resets 0000 000x 0000 ---0001 0011 uuuu uuuu uuuu uuuu 1111 1111 uuuu uuuu 1111 1111 1111 1111
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTB. This register is only initialized by a POR or BOR reset and is unchanged by other Resets. Configuration Word register bit DEBUG <12> is also associated with PORTB. See Register 16-1 for more details.
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3.5 PORTC and TRISC Registers
EXAMPLE 3-3:
BANKSEL CLRF BANKSEL MOVLW MOVWF BANKSEL CLRF PORTC PORTC TRISC 0FFh TRISC LCDCON LCDCON
INITIALIZING PORTC
; ;Init PORTC ; ;Set RC<7:0> as inputs ; ; ;Disable VLCD<3:1> ;inputs on RC<2:0>
PORTC is an 8-bit bidirectional port. PORTC is multiplexed with several peripheral functions. PORTC pins have Schmitt Trigger input buffers. All PORTC pins have latch bits (PORTC register). They will modify the contents of the PORTC latch (when written); thus, modifying the value driven out on a pin if the corresponding TRISC bit is configured for output.
REGISTER 3-8:
R/W-x RC7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
PORTC: PORTC REGISTER
R/W-x RC6 R/W-x RC5 R/W-x RC4 R/W-x RC3 R/W-x RC2 R/W-x RC1 R/W-x RC0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RC<7:0>: PORTC I/O Pin bits 1 = Port pin is >VIH min. 0 = Port pin is REGISTER 3-9:
R/W-1 TRISC7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
TRISC: PORTC TRI-STATE REGISTER
R/W-1 TRISC6 R/W-1 TRISC5 R/W-1 TRISC4 R/W-1 TRISC3 R/W-1 TRISC2 R/W-1 TRISC1 R/W-1 TRISC0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TRISC<7:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output
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3.5.1 PIN DESCRIPTIONS AND DIAGRAMS 3.5.1.3 RC2/VLCD3
Each PORTC pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the LCD or SSP, refer to the appropriate section in this data sheet. Figure 3-16 shows the diagram for this pin. The RC2 pin is configurable to function as one of the following: * a general purpose I/O * an analog input for the LCD bias voltage
3.5.1.1
RC0/VLCD1
Figure 3-14 shows the diagram for this pin. The RC0 pin is configurable to function as one of the following: * a general purpose I/O * an analog input for the LCD bias voltage
3.5.1.2
RC1/VLCD2
Figure 3-15 shows the diagram for this pin. The RC1 pin is configurable to function as one of the following: * a general purpose I/O * an analog input for the LCD bias voltage
FIGURE 3-14:
Data Bus WR PORTC
BLOCK DIAGRAM OF RC0
VDD
D
Q
Q CK Data Latch D Q Q VSS
I/O Pin
WR TRISC
CK
TRIS Latch (VLCDEN and LMUX<1:0> 00) RD TRISC Schmitt Trigger RD PORTC (LCDEN and LMUX<1:0> 00)
VLCD1
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FIGURE 3-15: BLOCK DIAGRAM OF RC1
Data Bus WR PORTC
D CK D
Q Q
VDD
Data Latch Q Q VSS
I/O Pin
WR TRISC
CK
TRIS Latch (VLCDEN and LMUX<1:0> 00) Schmitt Trigger RD PORTC (LCDEN and LMUX<1:0> 00)
RD TRISC
VLCD2
FIGURE 3-16:
BLOCK DIAGRAM OF RC2
VDD
Data Bus WR PORTC
D CK D
Q Q
Data Latch Q Q VSS
I/O Pin
WR TRISC
CK
TRIS Latch
VLCDEN RD TRISC Schmitt Trigger RD PORTC LCDEN
VLCD3
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3.5.1.4 RC3/SEG6
Figure 3-17 shows the diagram for this pin. The RC3 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
FIGURE 3-17:
BLOCK DIAGRAM OF RC3
Data Bus WR PORTC
D CK D
Q Q
VDD
Data Latch Q VSS
I/O Pin
WR TRISC
Q CK TRIS Latch
SE6 and LCDEN RD TRISC Schmitt Trigger RD PORTC SE6 and LCDEN
SEG6 and LCDEN
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3.5.1.5 RC4/T1G/SDO/SEG11
Figure 3-18 shows the diagram for this pin. The RC4pin is configurable to function as one of the following: * * * * a general purpose I/O a Timer1 gate input a serial data output an analog output for the LCD
FIGURE 3-18:
BLOCK DIAGRAM OF RC4
PORT/SDO Select SDO 0 1 VDD
Data Bus WR PORTC
D CK
Q
Q Data Latch D Q VSS CK Q TRIS Latch I/O Pin
WR TRISC
RD TRISC
SE11 and LCDEN
Schmitt Trigger
RD PORTC Timer1 Gate SEG11 SE11 and LCDEN
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3.5.1.6 RC5/T1CKI/CCP1/SEG10
Figure 3-19 shows the diagram for this pin. The RC5 pin is configurable to function as one of the following: * * * * a general purpose I/O a Timer1 clock input a Capture input, Compare output or PWM output an analog output for the LCD
FIGURE 3-19:
BLOCK DIAGRAM OF RC5
(PORT/CCP1 Select) and CCPMX CCP1 Data Out 0 Data Bus WR PORTC D CK D WR TRISC CK Q Q Q VSS Q TRIS Latch I/O Pin 1 VDD Data Latch
RD TRISC
SE10 and LCDEN
Schmitt Trigger
RD PORTC Timer1 Clock Input SEG10 SE10 and LCDEN
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3.5.1.7 RC6/TX/CK/SCK/SCL/SEG9
Figure 3-20 shows the diagram for this pin. The RC6 pin is configurable to function as one of the following: * * * * * * a general purpose I/O an asynchronous serial output a synchronous clock I/O a SPI clock I/O an I2C data I/O an analog output for the LCD
FIGURE 3-20:
BLOCK DIAGRAM OF RC6
PORT/USART/SSP Mode Select(1) I2CTM Data Out TX/CK Data Out SCK Data Out Data Bus WR PORTC D CK D WR TRISC CK Q VDD Q Q VSS Q TRIS Latch I/O Pin Data Latch
USART or I2CTM Drive
RD TRISC
SE9 and LCDEN
Schmitt Trigger
RD PORTC CK/SCL/SCK Input SEG9 SE9 and LCDEN
Note 1:
If all three data output sources are enabled, the following priority order will be used: * USART data (highest) * SSP data * PORT data (lowest)
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3.5.1.8 RC7/RX/DT/SDI/SDA/SEG8
Figure 3-21 shows the diagram for this pin. The RC7 pin is configurable to function as one of the following: * * * * * * a general purpose I/O an asynchronous serial input a synchronous serial data I/O a SPI data input an I2C data I/O an analog output for the LCD
FIGURE 3-21:
BLOCK DIAGRAM OF RC7
USART/I2CTM Mode Select(1) DT Data Out I2CTM Data Out
PORT/(USART or I2CTM) Select 0 1 Data Bus WR PORTC
VDD
I/O Pin VSS
D CK
Q Q
Data Latch D Q
WR TRISC
CK
Q
SE8 and LCDEN
TRIS Latch Schmitt Trigger
I2CTM Drive or SCEN Drive
RD TRISC
RD PORTC RX/SDI Input SEG8 Note 1: SE8 and LCDEN
If all three data output sources are enabled, the following priority order will be used: * USART data (highest) * SSP data * PORT data (lowest)
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TABLE 3-3:
Name CCP1CON LCDCON LCDSE0 LCDSE1 PORTC RCSTA SSPCON T1CON TRISC Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7 -- LCDEN SE7 SE15 RC7 SPEN WCOL T1GINV TRISC7 Bit 6 -- SLPEN SE6 SE14 RC6 RX9 SSPOV TMR1GE TRISC6 Bit 5 CCP1X WERR SE5 SE13 RC5 SREN SSPEN T1CKPS1 TRISC5 Bit 4 CCP1Y VLCDEN SE4 SE12 RC4 CREN CKP T1CKPS0 TRISC4 Bit 3 CCP1M3 CS1 SE3 SE11 RC3 ADDEN SSPM3 T1OSCEN TRISC3 Bit 2 CCP1M2 CS0 SE2 SE10 RC2 FERR SSPM2 T1SYNC TRISC2 Bit 1 CCP1M1 LMUX1 SE1 SE9 RC1 OERR SSPM1 TMR1CS TRISC1 Bit 0 CCP1M0 LMUX0 SE0 SE8 RC0 RX9D SSPM0 TMR1ON TRISC0 Value on POR, BOR --00 0000 0001 0011 0000 0000 0000 0000 xxxx xxxx 0000 000x 0000 0000 0000 0000 1111 1111 Value on all other Resets --00 0000 0001 0011 uuuu uuuu uuuu uuuu uuuu uuuu 0000 000x 0000 0000 uuuu uuuu 1111 1111
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTC.
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3.6 PORTD and TRISD Registers
EXAMPLE 3-4:
BANKSEL CLRF BANKSEL MOVLW MOVWF PORTD PORTD TRISD 0FF TRISD
INITIALIZING PORTD
; ;Init PORTD ; ;Set RD<7:0> as inputs ;
PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configured as an input or output. PORTD is only available on the PIC16F914/917 and PIC16F946.
REGISTER 3-10:
R/W-x RD7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
PORTD: PORTD REGISTER
R/W-x RD6 R/W-x RD5 R/W-x RD4 R/W-x RD3 R/W-x RD2 R/W-x RD1 R/W-x RD0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RD<7:0>: PORTD I/O Pin bits 1 = Port pin is >VIH min. 0 = Port pin is REGISTER 3-11:
R/W-1 TRISD7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
TRISD: PORTD TRI-STATE REGISTER
R/W-1 R/W-1 TRISD5 R/W-1 TRISD4 R/W-1 TRISD3 R/W-1 TRISD2 R/W-1 TRISD1 R/W-1 TRISD0 bit 0
TRISD6
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TRISD<7:0>: PORTD Tri-State Control bits 1 = PORTD pin configured as an input (tri-stated) 0 = PORTD pin configured as an output
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3.6.1 PIN DESCRIPTIONS AND DIAGRAMS 3.6.1.7 RD6/SEG19
Each PORTD pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the Comparator or the ADC, refer to the appropriate section in this data sheet. Figure 3-25 shows the diagram for this pin. The RD6 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
3.6.1.8
RD7/SEG20
3.6.1.1
RD0/COM3
Figure 3-22 shows the diagram for this pin. The RD0 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
Figure 3-25 shows the diagram for this pin. The RD7 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
3.6.1.2
RD1
Figure 3-23 shows the diagram for this pin. The RD1 pin is configurable to function as one of the following: * a general purpose I/O
3.6.1.3
RD2/CCP2
Figure 3-24 shows the diagram for this pin. The RD2 pin is configurable to function as one of the following: * a general purpose I/O * a Capture input, Compare output or PWM output
3.6.1.4
RD3/SEG16
Figure 3-25 shows the diagram for this pin. The RD3 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
3.6.1.5
RD4/SEG17
Figure 3-25 shows the diagram for this pin. The RD4 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
3.6.1.6
RD5/SEG18
Figure 3-25 shows the diagram for this pin. The RD5 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
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FIGURE 3-22: BLOCK DIAGRAM OF RD0
VDD Data Bus WR PORTD D CK
Q Q VSS I/O Pin
Data Latch D WR TRISD CK Q Q
TRIS Latch
RD TRISD
LCDEN and LMUX<1:0> = 11 Schmitt Trigger
RD PORTD LCDEN and LMUX<1:0> = 11
COM3
FIGURE 3-23:
BLOCK DIAGRAM OF RD1
VDD
Data Bus WR PORTD
D CK
Q Q VSS RD1 Pin
Data Latch D WR TRISD CK Q Q
TRIS Latch Schmitt Trigger
RD TRISD
RD PORTD
(c) 2007 Microchip Technology Inc.
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FIGURE 3-24: BLOCK DIAGRAM OF RD2
(PORT/CCP2 Select) and CCPMX VDD CCP2 Data Out 0 Data Bus WR PORTD
D CK D
Q Q Q Q
1 VSS
I/O Pin
Data Latch
WR TRISD
CK
TRIS Latch
Schmitt Trigger
RD TRISD
RD PORTD CCP2 Input
FIGURE 3-25:
BLOCK DIAGRAM OF RD<7:3>
VDD
Data Bus WR PORTD
D CK
Q Q VSS I/O Pin
Data Latch D WR TRISD CK Q Q
TRIS Latch SE<20:16> and LCDEN RD TRISD
Schmitt Trigger
RD PORTD SE<20:16> and LCDEN
SEG<20:16>
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TABLE 3-4:
Name CCP2CON(1) LCDCON LCDSE2(1) PORTD(1) TRISD(1) Legend: Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD(1)
Bit 7 -- LCDEN SE23 RD7 TRISD7 Bit 6 -- SLPEN SE22 RD6 TRISD6 Bit 5 CCP2X WERR SE21 RD5 TRISD5 Bit 4 CCP2Y VLCDEN SE20 RD4 TRISD4 Bit 3 CCP2M3 CS1 SE19 RD3 TRISD3 Bit 2 CCP2M2 CS0 SE18 RD2 TRISD2 Bit 1 CCP2M1 LMUX1 SE17 RD1 TRISD1 Bit 0 CCP2M0 LMUX0 SE16 RD0 TRISD0 Value on POR, BOR --00 0000 0001 0011 0000 0000 xxxx xxxx 1111 1111 Value on all other Resets --00 0000 0001 0011 uuuu uuuu uuuu uuuu 1111 1111
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTD. PIC16F914/917 and PIC16F946 only.
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3.7 PORTE and TRISE Registers
EXAMPLE 3-5:
BANKSEL CLRF BANKSEL MOVLW MOVWF CLRF PORTE PORTE TRISE 0Fh TRISE ANSEL
INITIALIZING PORTE
; ;Init PORTE ; ;Set RE<3:0> as inputs ; ;Make RE<2:0> as I/O's
PORTE is a 1-bit, 4-bit or 8-bit port with Schmitt Trigger input buffers. RE<7:4, 2:0> are individually configured as inputs or outputs and RE3 is only available as an input if MCLRE is `0' in Configuration Word (Register 16-1). RE<2:0> are only available on the PIC16F914/917 and PIC16F946. RE<7:4> are only available on the PIC16F946.
REGISTER 3-12:
R/W-x RE7(1,3) bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
PORTE: PORTE REGISTER
R/W-x R/W-x RE5(1,3) R/W-x RE4(1,3) R-x RE3 R/W-x RE2(2,4) R/W-x RE1(2,4) R/W-x RE0(2,4) bit 0
RE6(1,3)
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RE<7:0>: PORTE I/O Pin bits 1 = Port pin is >VIH min. 0 = Port pin is Note 1: 2: 3: 4:
REGISTER 3-13:
R/W-1 TRISE7(1,3) bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
TRISE: PORTE TRI-STATE REGISTER
R/W-1 R/W-1 TRISE5(1,3) R/W-1 TRISE4(1,3) R-1 TRISE3 R/W-1 TRISE2(2,4) R/W-1 TRISE1(2,4) R/W-1 TRISE0(2,4) bit 0
TRISE6(1,3)
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TRISE<7:0>: PORTE Tri-State Control bits 1 = PORTE pin configured as an input (tri-stated) 0 = PORTE pin configured as an output PIC16F946 only. PIC16F914/917 and PIC16F946 only. PIC16F91X, Read as `0'. PIC16F913/916, Read as `0'.
Note 1: 2: 3: 4:
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3.7.1 PIN DESCRIPTIONS AND DIAGRAMS 3.7.1.7 RE6/SEG26(2)
Each PORTE pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the Comparator or the ADC, refer to the appropriate section in this data sheet. Figure 3-28 shows the diagram for this pin. The RE6/SEG26 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
3.7.1.1
RE0/AN5/SEG21(1)
3.7.1.8
RE7/SEG27(2)
Figure 3-26 shows the diagram for this pin. The RE0 pin is configurable to function as one of the following: * a general purpose I/O * an analog input for the ADC * an analog output for the LCD
Figure 3-28 shows the diagram for this pin. The RE7/SEG27 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD Note 1: Pin is available on the PIC16F914/917 and PIC16F946 only. 2: Pin is available on the PIC16F946 only.
3.7.1.2
RE1/AN6/SEG22(1)
Figure 3-26 shows the diagram for this pin. The RE1 pin is configurable to function as one of the following: * a general purpose I/O * an analog input for the ADC * an analog output for the LCD
3.7.1.3
RE2/AN7/SEG23(1)
Figure 3-26 shows the diagram for this pin. The RE2 pin is configurable to function as one of the following: * a general purpose I/O * an analog input for the ADC * an analog output for the LCD
3.7.1.4
RE3/MCLR/VPP
Figure 3-27 shows the diagram for this pin. The RE3 pin is configurable to function as one of the following: * a digital input only * as Master Clear Reset with weak pull-up * a programming voltage reference input
3.7.1.5
RE4/SEG24(2)
Figure 3-28 shows the diagram for this pin. The RE4/SEG24 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
3.7.1.6
RE5/SEG25(2)
Figure 3-28 shows the diagram for this pin. The RE5/SEG25 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
(c) 2007 Microchip Technology Inc.
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FIGURE 3-26: BLOCK DIAGRAM OF RE<2:0> (PIC16F914/917 AND PIC16F946 ONLY)
VDD Data Bus WR PORTE D CK Q Q VSS I/O Pin
Data Latch D WR TRISE CK Q Q Analog Mode or RD TRISE SEG<23:21> and LCDEN Schmitt and LCDEN Trigger
TRIS Latch
RD PORTE SEG<23:21> AN<7:5> SEG<23:21> and LCDEN
FIGURE 3-27:
BLOCK DIAGRAM OF RE3
HV Schmitt Trigger Buffer
MCLR circuit
MCLR Filter
Programming mode
HV Detect MCLRE Input Pin VSS HV Schmitt Trigger Buffer
Data Bus RD TRISE VSS
RD PORTE
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FIGURE 3-28: BLOCK DIAGRAM OF RE<7:4> (PIC16F946 ONLY)
VDD Data Bus WR PORTE D CK Q Q VSS I/O Pin
Data Latch D WR TRISE CK Q Q Analog Mode or RD TRISE SEG<27:24> and LCDEN Schmitt Trigger
TRIS Latch
RD PORTE SEG<27:24> AN<7:5> SEG<27:24> and LCDEN
(c) 2007 Microchip Technology Inc.
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TABLE 3-5:
Name ADCON0 ANSEL LCDCON LCDSE2(1,2) LCDSE3(1, 3) PORTE TRISE Legend: Note 1: 2: 3: 4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Bit 7 ADFM ANS7 LCDEN SE23 SE31 RE7(3) Bit 6 VCFG1 ANS6 SLPEN SE22 SE30 RE6(3) TRISE6(3) Bit 5 VCFG0 ANS5 WERR SE21 SE29 RE5(3) TRISE5(3) Bit 4 CHS2 ANS4 VLCDEN SE20 SE28 RE4(3) TRISE4(3) Bit 3 CHS1 ANS3 CS1 SE19 SE27 RE3 TRISE3(4) Bit 2 CHS0 ANS2 CS0 SE18 SE26 RE2(2) TRISE2(2) Bit 1 GO/DONE ANS1 LMUX1 SE17 SE25 RE1(2) TRISE1(2) Bit 0 ADON ANS0 LMUX0 SE16 SE24 RE0(2) TRISE0(2) Value on POR, BOR 0000 0000 1111 1111 0001 0011 0000 0000 0000 0000 xxxx xxxx 1111 1111 Value on all other Resets 0000 0000 1111 1111 0001 0011 uuuu uuuu uuuu uuuu uuuu uuuu 1111 1111
TRISE7(3)
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTC. This register is only initialized by a POR or BOR reset and is unchanged by other Resets. PIC16F914/917 and PIC16F946 only. PIC16F946 only. Bit is read-only; TRISE = 1 always.
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3.8 PORTF and TRISF Registers
EXAMPLE 3-6:
BANKSEL CLRF BANKSEL MOVLW MOVWF PORTF PORTF TRISF 0FFh TRISF
INITIALIZING PORTF
; ;Init PORTF ; ;Set RF<7:0> as inputs ;
PORTF is an 8-bit port with Schmitt Trigger input buffers. RF<7:0> are individually configured as inputs or outputs, depending on the state of the port direction. The port bits are also multiplexed with LCD segment functions. PORTF is available on the PIC16F946 only.
REGISTER 3-14:
R/W-x RF7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
PORTF: PORTF REGISTER(1)
R/W-x RF6 R/W-x RF5 R/W-x RF4 R/W-x RF3 R/W-x RF2 R/W-x RF1 R/W-x RF0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RF<7:0>: PORTF I/O Pin bits 1 = Port pin is >VIH min. 0 = Port pin is Note 1:
REGISTER 3-15:
R/W-1 TRISF7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
TRISF: PORTF TRI-STATE REGISTER(1)
R/W-1 R/W-1 TRISF5 R/W-1 TRISF4 R/W-1 TRISF3 R/W-1 TRISF2 R/W-1 TRISF1 R/W-1 TRISF0 bit 0
TRISF6
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TRISF<7:0>: PORTF Tri-State Control bits 1 = PORTF pin configured as an input (tri-stated) 0 = PORTF pin configured as an output PIC16F946 only.
Note 1:
(c) 2007 Microchip Technology Inc.
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3.8.1 PIN DESCRIPTIONS AND DIAGRAMS 3.8.1.7 RF6/SEG30
Each PORTF pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions, refer to the appropriate section in this data sheet. Figure 3-29 shows the diagram for this pin. The RF6 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
3.8.1.1
RF0/SEG32
3.8.1.8
RF7/SEG31
Figure 3-29 shows the diagram for this pin. The RF0 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
Figure 3-29 shows the diagram for this pin. The RF7 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
3.8.1.2
RF1/SEG33
Figure 3-29 shows the diagram for this pin. The RF1 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
3.8.1.3
RF2/SEG34
Figure 3-29 shows the diagram for this pin. The RF2 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
3.8.1.4
RF3/SEG35
Figure 3-29 shows the diagram for this pin. The RF3 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
3.8.1.5
RF4/SEG28
Figure 3-29 shows the diagram for this pin. The RF4 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
3.8.1.6
RF5/SEG29
Figure 3-29 shows the diagram for this pin. The RF5 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
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FIGURE 3-29: BLOCK DIAGRAM OF RF<7:0>
VDD Data Bus WR PORTF D CK Q Q VSS I/O Pin
Data Latch D WR TRISF CK Q Q
TRIS Latch
RD TRISF
SE<35:28> and LCDEN
Schmitt Trigger
RD PORTF SEG<35:28> SE<35:28> and LCDEN
TABLE 3-6:
Name LCDCON LCDSE3
(1)
SUMMARY OF REGISTERS ASSOCIATED WITH PORTF(1)
Bit 7 Bit 6 SLPEN SE30 SE38 RF6 TRISF6 Bit 5 WERR SE29 SE37 RF5 TRISF5 Bit 4 VLCDEN SE28 SE36 RF4 TRISF4 Bit 3 CS1 SE27 SE35 RF3 TRISF3 Bit 2 CS0 SE26 SE34 RF2 TRISF2 Bit 1 LMUX1 SE25 SE33 RF1 TRISF1 Bit 0 LMUX0 SE24 SE32 RF0 TRISF0 Value on POR, BOR 0001 0011 0000 0000 0000 0000 xxxx xxxx 1111 1111 Value on all other Resets 0001 0011 uuuu uuuu uuuu uuuu uuuu uuuu 1111 1111
LCDEN SE31 SE39 RF7 TRISF7
LCDSE4(1) PORTF(1) TRISF(1) Legend: Note 1:
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTF. PIC16F946 only.
(c) 2007 Microchip Technology Inc.
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3.9 PORTG and TRISG Registers
EXAMPLE 3-7:
BANKSEL CLRF BANKSEL MOVLW MOVWF PORTG PORTG TRISG 3Fh TRISG
INITIALIZING PORTG
; ;Init PORTG ; ;Set RG<5:0> as inputs ;
PORTG is an 8-bit port with Schmitt Trigger input buffers. RG<5:0> are individually configured as inputs or outputs, depending on the state of the port direction. The port bits are also multiplexed with LCD segment functions. PORTG is available on the PIC16F946 only.
REGISTER 3-16:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
PORTG: PORTG REGISTER(1)
U-0 -- R/W-x RG5 R/W-x RG4 R/W-x RG3 R/W-x RG2 R/W-x RG1 R/W-x RG0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' RG<5:0>: PORTG I/O Pin bits 1 = Port pin is >VIH min. 0 = Port pin is Note 1:
REGISTER 3-17:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
TRISG: PORTG TRI-STATE REGISTER(1)
U-0 -- R/W-1 TRISG5 R/W-1 TRISG4 R/W-1 TRISG3 R/W-1 TRISG2 R/W-1 TRISG1 R/W-1 TRISG0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' TRISF<5:0>: PORTG Tri-State Control bits 1 = PORTG pin configured as an input (tri-stated) 0 = PORTG pin configured as an output PIC16F946 only.
Note 1:
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3.9.1 PIN DESCRIPTIONS AND DIAGRAMS 3.9.1.4 RG3/SEG39
Each PORTG pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions, refer to the appropriate section in this data sheet. Figure 3-30 shows the diagram for this pin. The RG3 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
3.9.1.1
RG0/SEG36
3.9.1.5
RG4/SEG40
Figure 3-30 shows the diagram for this pin. The RG0 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
Figure 3-30 shows the diagram for this pin. The RG4 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
3.9.1.2
RG1/SEG37
3.9.1.6
RG5/SEG41
Figure 3-30 shows the diagram for this pin. The RG1 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
Figure 3-30 shows the diagram for this pin. The RG5 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
3.9.1.3
RG2/SEG38
Figure 3-30 shows the diagram for this pin. The RG2 pin is configurable to function as one of the following: * a general purpose I/O * an analog output for the LCD
FIGURE 3-30:
BLOCK DIAGRAM OF RG<5:0>
VDD
Data Bus WR PORTG
D CK
Q Q VSS I/O Pin
Data Latch D WR TRISG CK Q Q
TRIS Latch
RD TRISG
SE<41:36> and LCDEN
Schmitt Trigger
RD PORTG SEG<41:36> SE<41:36> and LCDEN
(c) 2007 Microchip Technology Inc.
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TABLE 3-7:
Name LCDCON LCDSE4(1) LCDSE5(1) PORTG(1) TRISG
(1)
SUMMARY OF REGISTERS ASSOCIATED WITH PORTG(1)
Bit 7 Bit 6 SLPEN SE38 -- -- -- Bit 5 WERR SE37 -- RG5 TRISG5 Bit 4 VLCDEN SE36 -- RG4 TRISG4 Bit 3 CS1 SE35 -- RG3 TRISG3 Bit 2 CS0 SE34 -- RG2 TRISG2 Bit 1 LMUX1 SE33 SE41 RG1 TRISG1 Bit 0 LMUX0 SE32 SE40 RG0 TRISG0 Value on POR, BOR 0001 0011 0000 0000 ---- --00 --xx xxxx --11 1111 Value on all other Resets 0001 0011 uuuu uuuu ---- --uu --uu uuuu --11 1111
LCDEN SE39 -- -- --
Legend: Note 1:
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTG. PIC16F946 only.
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4.0
4.1
OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR)
Overview
The Oscillator module can be configured in one of eight clock modes. 1. 2. 3. 4. 5. 6. 7. 8. EC - External clock with I/O on OSC2/CLKOUT. LP - 32 kHz Low-Power Crystal mode. XT - Medium Gain Crystal or Ceramic Resonator Oscillator mode. HS - High Gain Crystal or Ceramic Resonator mode. RC - External Resistor-Capacitor (RC) with FOSC/4 output on OSC2/CLKOUT. RCIO - External Resistor-Capacitor (RC) with I/O on OSC2/CLKOUT. INTOSC - Internal oscillator with FOSC/4 output on OSC2 and I/O on OSC1/CLKIN. INTOSCIO - Internal oscillator with I/O on OSC1/CLKIN and OSC2/CLKOUT.
The Oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 4-1 illustrates a block diagram of the Oscillator module. Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured from one of two internal oscillators, with a choice of speeds selectable via software. Additional clock features include: * Selectable system clock source between external or internal via software. * Two-Speed Start-up mode, which minimizes latency between external oscillator start-up and code execution. * Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator.
Clock Source modes are configured by the FOSC<2:0> bits in the Configuration Word register (CONFIG). The internal clock can be generated from two internal oscillators. The HFINTOSC is a calibrated high-frequency oscillator. The LFINTOSC is an uncalibrated low-frequency oscillator.
FIGURE 4-1:
SIMPLIFIED PIC(R) MCU CLOCK SOURCE BLOCK DIAGRAM
FOSC<2:0> (Configuration Word Register) SCS<0> (OSCCON Register)
External Oscillator OSC2 Sleep OSC1
LP, XT, HS, RC, RCIO, EC MUX INTOSC
IRCF<2:0> (OSCCON Register) 8 MHz Internal Oscillator 4 MHz 2 MHz Postscaler HFINTOSC 8 MHz 100 011 010 001 000 MUX 1 MHz 500 kHz 250 kHz 125 kHz LFINTOSC 31 kHz 31 kHz 101 111 110
System Clock (CPU and Peripherals)
Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM)
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4.2 Oscillator Control
The Oscillator Control (OSCCON) register (Figure 4-1) controls the system clock and frequency selection options. The OSCCON register contains the following bits: * Frequency selection bits (IRCF) * Frequency Status bits (HTS, LTS) * System clock control bits (OSTS, SCS)
REGISTER 4-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-4
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-1 IRCF2 R/W-1 IRCF1 R/W-0 IRCF0 R-1 OSTS(1) R-0 HTS R-0 LTS R/W-0 SCS bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' IRCF<2:0>: Internal Oscillator Frequency Select bits 111 = 8 MHz 110 = 4 MHz (default) 101 = 2 MHz 100 = 1 MHz 011 = 500 kHz 010 = 250 kHz 001 = 125 kHz 000 = 31 kHz (LFINTOSC) OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Device is running from the clock defined by FOSC<2:0> of the Configuration Word 0 = Device is running from the internal oscillator (HFINTOSC or LFINTOSC) HTS: HFINTOSC Status bit (High Frequency - 8 MHz to 125 kHz) 1 = HFINTOSC is stable 0 = HFINTOSC is not stable LTS: LFINTOSC Stable bit (Low Frequency - 31 kHz) 1 = LFINTOSC is stable 0 = LFINTOSC is not stable SCS: System Clock Select bit 1 = Internal oscillator is used for system clock 0 = Clock source defined by FOSC<2:0> of the Configuration Word Bit resets to `0' with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled.
bit 3
bit 2
bit 1
bit 0
Note 1:
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4.3 Clock Source Modes 4.4
4.4.1
External Clock Modes
OSCILLATOR START-UP TIMER (OST)
Clock Source modes can be classified as external or internal. * External Clock modes rely on external circuitry for the clock source. Examples are: Oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. * Internal clock sources are contained internally within the Oscillator module. The Oscillator module has two internal oscillators: the 8 MHz High-Frequency Internal Oscillator (HFINTOSC) and the 31 kHz Low-Frequency Internal Oscillator (LFINTOSC). The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bit of the OSCCON register. See Section 4.6 "Clock Switching" for additional information.
If the Oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the Oscillator module. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 4-1. In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 4.7 "Two-Speed Clock Start-up Mode").
TABLE 4-1:
OSCILLATOR DELAY EXAMPLES
Switch To LFINTOSC HFINTOSC EC, RC EC, RC LP, XT, HS HFINTOSC Frequency 31 kHz 125 kHz to 8 MHz DC - 20 MHz DC - 20 MHz 32 kHz to 20 MHz 125 kHz to 8 MHz Oscillator Delay Oscillator Warm-Up Delay (TWARM) 2 instruction cycles 1 cycle of each 1024 Clock Cycles (OST) 1 s (approx.)
Switch From Sleep/POR Sleep/POR LFINTOSC (31 kHz) Sleep/POR LFINTOSC (31 kHz)
4.4.2
EC MODE
FIGURE 4-2:
The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input and the OSC2 is available for general purpose I/O. Figure 4-2 shows the pin connections for EC mode. The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC(R) MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.
EXTERNAL CLOCK (EC) MODE OPERATION
OSC1/CLKIN PIC(R) MCU I/O OSC2/CLKOUT(1)
Clock from Ext. System
Note 1:
Alternate pin functions are listed in Section 1.0 "Device Overview".
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4.4.3 LP, XT, HS MODES
The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 4-3). The mode selects a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals). XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification. HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting. Figure 4-3 and Figure 4-4 show typical circuits for quartz crystal and ceramic resonators, respectively. Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Applications Notes: * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPIC(R) and PIC(R) Devices" (DS00826) * AN849, "Basic PIC(R) Oscillator Design" (DS00849) * AN943, "Practical PIC(R) Oscillator Analysis and Design" (DS00943) * AN949, "Making Your Oscillator Work" (DS00949)
FIGURE 4-4:
CERAMIC RESONATOR OPERATION (XT OR HS MODE)
PIC(R) MCU
OSC1/CLKIN
FIGURE 4-3:
QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE)
PIC(R) MCU
OSC1/CLKIN C1
To Internal Logic RP(3) RF(2) Sleep
C1 Quartz Crystal RF(2)
To Internal Logic Sleep C2 Ceramic RS(1) Resonator OSC2/CLKOUT
C2
RS(1)
OSC2/CLKOUT
Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M). 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation.
Note 1: 2:
A series resistor (RS) may be required for quartz crystals with low drive level. The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M).
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4.4.4 EXTERNAL RC MODES
4.5
Internal Clock Modes
The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO. In RC mode, the RC circuit connects to OSC1. OSC2/CLKOUT outputs the RC oscillator frequency divided by 4. This signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. Figure 4-5 shows the external RC mode connections.
The Oscillator module has two independent, internal oscillators that can be configured or selected as the system clock source. 1. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 8 MHz. The frequency of the HFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 4-2). The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at 31 kHz.
2.
FIGURE 4-5:
VDD REXT
EXTERNAL RC MODES
PIC(R) MCU
The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<2:0> of the OSCCON register. The system clock can be selected between external or internal clock sources via the System Clock Selection (SCS) bit of the OSCCON register. See Section 4.6 "Clock Switching" for more information.
OSC1/CLKIN CEXT VSS FOSC/4 or I/O(2) OSC2/CLKOUT(1)
Internal Clock
4.5.1
INTOSC AND INTOSCIO MODES
Recommended values: 10 k REXT 100 k, <3V 3 k REXT 100 k, 3-5V CEXT > 20 pF, 2-5V Note 1: 2: Alternate pin functions are listed in Section 1.0 "Device Overview". Output depends upon RC or RCIO clock mode.
The INTOSC and INTOSCIO modes configure the internal oscillators as the system clock source when the device is programmed using the oscillator selection or the FOSC<2:0> bits in the Configuration Word register (CONFIG). See Section 16.0 "Special Features of the CPU" for more information. In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT outputs the selected internal oscillator frequency divided by 4. The CLKOUT signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT are available for general purpose I/O.
In RCIO mode, the RC circuit is connected to OSC1. OSC2 becomes an additional general purpose I/O pin. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are: * threshold voltage variation * component tolerances * packaging variations in capacitance The user also needs to take into account variation due to tolerance of external RC components used.
4.5.2
HFINTOSC
The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 8 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 4-2). The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 4-1). One of seven frequencies can be selected via software using the IRCF<2:0> bits of the OSCCON register. See Section 4.5.4 "Frequency Select Bits (IRCF)" for more information. The HFINTOSC is enabled by selecting any frequency between 8 MHz and 125 kHz by setting the IRCF<2:0> bits of the OSCCON register 000. Then, set the System Clock Source (SCS) bit of the OSCCON register to `1' or enable Two-Speed Start-up by setting the IESO bit in the Configuration Word register (CONFIG) to `1'. The HF Internal Oscillator (HTS) bit of the OSCCON register indicates whether the HFINTOSC is stable or not.
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4.5.2.1 OSCTUNE Register
The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 4-2). The default value of the OSCTUNE register is `0'. The value is a 5-bit two's complement number. When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency.
REGISTER 4-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0
OSCTUNE: OSCILLATOR TUNING REGISTER
U-0 -- U-0 -- R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' TUN<4:0>: Frequency Tuning bits 01111 = Maximum frequency 01110 = * * * 00001 = 00000 = Oscillator module is running at the factory-calibrated frequency. 11111 = * * * 10000 = Minimum frequency
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4.5.3 LFINTOSC 4.5.5
The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 4-1). Select 31 kHz, via software, using the IRCF<2:0> bits of the OSCCON register. See Section 4.5.4 "Frequency Select Bits (IRCF)" for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled by selecting 31 kHz (IRCF<2:0> bits of the OSCCON register = 000) as the system clock source (SCS bit of the OSCCON register = 1), or when any of the following are enabled: * Two-Speed Start-up IESO bit of the Configuration Word register = 1 and IRCF<2:0> bits of the OSCCON register = 000 * Power-up Timer (PWRT) * Watchdog Timer (WDT) * Fail-Safe Clock Monitor (FSCM) The LF Internal Oscillator (LTS) bit of the OSCCON register indicates whether the LFINTOSC is stable or not.
HF AND LF INTOSC CLOCK SWITCH TIMING
When switching between the LFINTOSC and the HFINTOSC, the new oscillator may already be shut down to save power (see Figure 4-6). If this is the case, there is a delay after the IRCF<2:0> bits of the OSCCON register are modified before the frequency selection takes place. The LTS and HTS bits of the OSCCON register will reflect the current active status of the LFINTOSC and HFINTOSC oscillators. The timing of a frequency selection is as follows: 1. 2. 3. 4. 5. IRCF<2:0> bits of the OSCCON register are modified. If the new clock is shut down, a clock start-up delay is started. Clock switch circuitry waits for a falling edge of the current clock. CLKOUT is held low and the clock switch circuitry waits for a rising edge in the new clock. CLKOUT is now connected with the new clock. LTS and HTS bits of the OSCCON register are updated as required. Clock switch is complete.
6.
See Figure 4-1 for more details. If the internal oscillator speed selected is between 8 MHz and 125 kHz, there is no start-up delay before the new frequency is selected. This is because the old and new frequencies are derived from the HFINTOSC via the postscaler and multiplexer. Start-up delay specifications are located under the oscillator parameters of Section 19.0 "Electrical Specifications".
4.5.4
FREQUENCY SELECT BITS (IRCF)
The output of the 8 MHz HFINTOSC and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 4-1). The Internal Oscillator Frequency Select bits IRCF<2:0> of the OSCCON register select the frequency output of the internal oscillators. One of eight frequencies can be selected via software: * * * * * * * * 8 MHz 4 MHz (Default after Reset) 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 31 kHz (LFINTOSC) Note: Following any Reset, the IRCF<2:0> bits of the OSCCON register are set to `110' and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency.
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FIGURE 4-6: INTERNAL OSCILLATOR SWITCH TIMING
HFINTOSC HFINTOSC
LFINTOSC (FSCM and WDT disabled)
Start-up Time
2-cycle Sync
Running
LFINTOSC IRCF <2:0> System Clock 0 =0
HFINTOSC HFINTOSC
LFINTOSC (Either FSCM or WDT enabled)
2-cycle Sync
Running
LFINTOSC IRCF <2:0> System Clock
0
=0
LFINTOSC LFINTOSC
HFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
Start-up Time 2-cycle Sync
Running
HFINTOSC IRCF <2:0> System Clock =0
0
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4.6 Clock Switching
The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bit of the OSCCON register. When the Oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) is enabled (see Section 4.4.1 "Oscillator Start-up Timer (OST)"). The OST will suspend program execution until 1024 oscillations are counted. Two-Speed Start-up mode minimizes the delay in code execution by operating from the internal oscillator as the OST is counting. When the OST count reaches 1024 and the OSTS bit of the OSCCON register is set, program execution switches to the external oscillator.
4.6.1
SYSTEM CLOCK SELECT (SCS) BIT
The System Clock Select (SCS) bit of the OSCCON register selects the system clock source that is used for the CPU and peripherals. * When the SCS bit of the OSCCON register = 0, the system clock source is determined by configuration of the FOSC<2:0> bits in the Configuration Word register (CONFIG). * When the SCS bit of the OSCCON register = 1, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<2:0> bits of the OSCCON register. After a Reset, the SCS bit of the OSCCON register is always cleared. Note: Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bit of the OSCCON register. The user can monitor the OSTS bit of the OSCCON register to determine the current system clock source.
4.7.1
TWO-SPEED START-UP MODE CONFIGURATION
Two-Speed Start-up mode is configured by the following settings: * IESO (of the Configuration Word register) = 1; Internal/External Switchover bit (Two-Speed Start-up mode enabled). * SCS (of the OSCCON register) = 0. * FOSC<2:0> bits in the Configuration Word register (CONFIG) configured for LP, XT or HS mode. Two-Speed Start-up mode is entered after: * Power-on Reset (POR) and, if enabled, after Power-up Timer (PWRT) has expired, or * Wake-up from Sleep. If the external clock oscillator is configured to be anything other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep.
4.6.2
OSCILLATOR START-UP TIME-OUT STATUS (OSTS) BIT
The Oscillator Start-up Time-out Status (OSTS) bit of the OSCCON register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word register (CONFIG), or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes.
4.7.2
1. 2.
TWO-SPEED START-UP SEQUENCE
4.7
Two-Speed Clock Start-up Mode
Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC as the clock source and go back to Sleep without waiting for the primary oscillator to become stable. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCCON register to remain clear.
3. 4. 5. 6. 7.
Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<2:0> bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source.
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4.7.3 CHECKING TWO-SPEED CLOCK STATUS
Checking the state of the OSTS bit of the OSCCON register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word register (CONFIG), or the internal oscillator.
FIGURE 4-7:
TWO-SPEED START-UP
HFINTOSC T TOST OSC1 0 1 1022 1023
OSC2 Program Counter PC - N PC PC + 1
System Clock
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4.8 Fail-Safe Clock Monitor
4.8.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Word register (CONFIG). The FSCM is applicable to all external oscillator modes (LP, XT, HS, EC, RC and RCIO). The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or toggling the SCS bit of the OSCCON register. When the SCS bit is toggled, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared and the device will be operating from the external clock source. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared.
FIGURE 4-8:
FSCM BLOCK DIAGRAM
Clock Monitor Latch S Q
4.8.4
RESET OR WAKE-UP FROM SLEEP
External Clock
LFINTOSC Oscillator 31 kHz (~32 s)
/ 64 488 Hz (~2 ms)
R
Q
The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. When the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing code while the OST is operating. Note:
Clock Failure Detected
Sample Clock
4.8.1
FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 4-8. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the primary clock goes low.
Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the OSTS bit of the OSCCON register to verify the oscillator start-up and that the system clock switchover has successfully completed.
4.8.2
FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. The internal clock source chosen by the FSCM is determined by the IRCF<2:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.
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FIGURE 4-9:
Sample Clock System Clock Output Clock Monitor Output (Q) OSCFIF Oscillator Failure
FSCM TIMING DIAGRAM
Failure Detected
Test Note:
Test
Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.
TABLE 4-2:
Name CONFIG(2) INTCON OSCCON OSCTUNE PIE2 PIR2 T1CON Legend: Note 1: 2:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Bit 7 CPD GIE -- -- OSFIE OSFIF T1GINV Bit 6 CP PEIE IRCF2 -- C2IE C2IF TMR1GE Bit 5 MCLRE T0IE IRCF1 -- C1IE C1IF T1CKPS1 Bit 4 PWRTE INTE IRCF0 TUN4 LCDIE LCDIF T1CKPS0 Bit 3 WDTE RBIE OSTS TUN3 -- -- T1OSCEN Bit 2 FOSC2 T0IF HTS TUN2 LVDIE LVDIF T1SYNC Bit 1 FOSC1 INTF LTS TUN1 -- -- TMR1CS Bit 0 FOSC0 RBIF SCS TUN0 CCP2IE CCP2IF TMR1ON Value on POR, BOR -- 0000 000x -110 x000 ---0 0000 0000 -0-0 0000 -0-0 0000 0000 Value on all other Resets(1) -- 0000 000x -110 x000 ---u uuuu 0000 -0-0 0000 -0-0 0000 0000
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by oscillators. Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. See Configuration Word register (CONFIG) for operation of all register bits.
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5.0 TIMER0 MODULE
5.1 Timer0 Operation
The Timer0 module is an 8-bit timer/counter with the following features: * * * * * 8-bit timer/counter register (TMR0) 8-bit prescaler (shared with Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter.
5.1.1
8-BIT TIMER MODE
When used as a timer, the Timer0 module will increment every instruction cycle (without prescaler). Timer mode is selected by clearing the T0CS bit of the OPTION register to `0'. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written.
Figure 5-1 is a block diagram of the Timer0 module.
5.1.2
8-BIT COUNTER MODE
When used as a counter, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. The incrementing edge is determined by the T0SE bit of the Option register. Counter mode is selected by setting the T0CS bit of the Option register to `1'.
FIGURE 5-1:
FOSC/4
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 0 1 1 T0CKI pin T0SE T0CS 0 0 8-bit Prescaler 1 8 PSA Set Flag bit T0IF on Overflow Sync 2 Tcy TMR0 8
WDTE SWDTEN
PSA
PS<2:0> 16-bit Prescaler 31 kHz INTOSC Watchdog Timer WDTPS<3:0>
Note 1: 2: 3: T0SE, T0CS, PSA, PS<2:0> are bits in the Option register. SWDTEN and WDTPS<3:0> are bits in the WDTCON register. WDTE bit is in the Configuration Word register.
1 WDT Time-out
16
0
PSA
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5.1.3 SOFTWARE PROGRAMMABLE PRESCALER
A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the Option register. To assign the prescaler to Timer0, the PSA bit must be cleared to a `0'. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be assigned to the WDT module. The prescaler is not readable or writable. When assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the prescaler. When the prescaler is assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. When changing the prescaler assignment from the WDT to the Timer0 module, the following instruction sequence must be executed (see Example 5-2).
EXAMPLE 5-2:
CLRWDT
CHANGING PRESCALER (WDT TIMER0)
;Clear WDT and ;prescaler BANKSEL OPTION_REG ; MOVLW b'11110000' ;Mask TMR0 select and ANDWF OPTION_REG,W ;prescaler bits IORLW b'00000011' ;Set prescale to 1:16 MOVWF OPTION_REG ;
5.1.4
TIMER0 INTERRUPT
5.1.3.1
Switching Prescaler Between Timer0 and WDT Modules
Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The T0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The T0IF bit must be cleared in software. The Timer0 interrupt enable is the T0IE bit of the INTCON register. Note: The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep.
As a result of having the prescaler assigned to either Timer0 or the WDT, it is possible to generate an unintended device Reset when switching prescaler values. When changing the prescaler assignment from Timer0 to the WDT module, the instruction sequence shown in Example 5-1, must be executed.
5.1.5
USING TIMER0 WITH AN EXTERNAL CLOCK
EXAMPLE 5-1:
BANKSEL CLRWDT CLRF BANKSEL BSF CLRWDT MOVLW ANDWF IORLW MOVWF TMR0 TMR0
CHANGING PRESCALER (TIMER0 WDT)
; ;Clear WDT ;Clear TMR0 and ;prescaler ; ;Select WDT ; ; ;Mask prescaler ;bits ;Set WDT prescaler ;to 1:32
When Timer0 is in Counter mode, the synchronization of the T0CKI input and the Timer0 register is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements as shown in Section 19.0 "Electrical Specifications"
OPTION_REG OPTION_REG,PSA
b'11111000' OPTION_REG,W b'00000101' OPTION_REG
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REGISTER 5-1:
R/W-1 RBPU bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
OPTION_REG: OPTION REGISTER
R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual PORT latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits
BIT VALUE 000 001 010 011 100 101 110 111 TMR0 RATE 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT RATE 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1:
A dedicated 16-bit WDT postscaler is available. See Section 16.4 "Watchdog Timer (WDT)" for more information.
TABLE 5-1:
Name TMR0 INTCON OPTION_REG TRISA
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets
Timer0 Module Register GIE PEIE T0IE T0CS INTE T0SE RBIE PSA T0IF PS2 INTF PS1 RBIF PS0 RBPU INTEDG
xxxx xxxx uuuu uuuu 0000 000x 0000 000x 1111 1111 1111 1111
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
Legend: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.
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6.0 TIMER1 MODULE WITH GATE CONTROL
6.1 Timer1 Operation
The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer. When used with an external clock source, the module can be used as either a timer or counter.
The Timer1 module is a 16-bit timer/counter with the following features: 16-bit timer/counter register pair (TMR1H:TMR1L) Programmable internal or external clock source 3-bit prescaler Optional LP oscillator Synchronous or asynchronous operation Timer1 gate (count enable) via comparator or T1G pin * Interrupt on overflow * Wake-up on overflow (external clock, Asynchronous mode only) * Clock source for LCD module Figure 6-1 is a block diagram of the Timer1 module. * * * * * *
6.2
Clock Source Selection
The TMR1CS bit of the T1CON register is used to select the clock source. When TMR1CS = 0, the clock source is FOSC/4. When TMR1CS = 1, the clock source is supplied externally.
Clock Source FOSC/4 T1CKI pin
TMR1CS 0 1
FIGURE 6-1:
TIMER1 BLOCK DIAGRAM
TMR1GE TMR1ON
T1GINV
Set flag bit TMR1IF on Overflow
TMR1(2) TMR1H LP OSC TMR1L EN
To C2 Comparator Module Timer1 Clock 0 Synchronized clock input
To LCD Module
(1)
1 T1SYNC
OSC1/T1OSI
1 1 0
OSC2/T1OSO FOSC = 000 FOSC = x00 T1OSCEN T1CKI
FOSC/4 Internal Clock
Prescaler 1, 2, 4, 8 0 2 T1CKPS<1:0> T1G SYNCC2OUT(4)
Synchronize(3) det
TMR1CS
1 0 T1GSS
Note 1: 2: 3: 4:
ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI. Timer1 register increments on rising edge. Synchronize does not operate while in Sleep. SYNCC2OUT is synchronized when the C2SYNC bit of the CMCON1 register is set.
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6.2.1 INTERNAL CLOCK SOURCE
6.5
When the internal clock source is selected, the TMR1H:TMR1L register pair will increment on multiples of TCY as determined by the Timer1 prescaler.
Timer1 Operation in Asynchronous Counter Mode
6.2.2
EXTERNAL CLOCK SOURCE
When the external clock source is selected, the Timer1 module may work as a timer or a counter. When counting, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after one or more of the following conditions: * Timer1 is enabled after POR or BOR Reset * A write to TMR1H or TMR1L * T1CKI is high when Timer1 is disabled and when Timer1 is reenabled T1CKI is low. See Figure 6-2.
If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 6.5.1 "Reading and Writing Timer1 in Asynchronous Counter Mode"). Note 1: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment.
6.5.1
6.3
Timer1 Prescaler
READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE
Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L.
Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair.
6.4
Timer1 Oscillator
A low-power 32.768 kHz crystal oscillator is built-in between pins OSC1 (input) and OSC2 (amplifier output). The oscillator is enabled by setting the T1OSCEN control bit of the T1CON register. The oscillator will continue to run during Sleep. The Timer1 oscillator is shared with the system LP oscillator. Thus, Timer1 can use this mode only when the primary system clock is derived from the internal oscillator or when in LP oscillator mode. The user must provide a software time delay to ensure proper oscillator start-up. TRISA7 and TRISA6 bits are set when the Timer1 oscillator is enabled. RA7 and RA6 bits read as `0' and TRISA7 and TRISA6 bits read as `1'. Note: The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1.
6.6
Timer1 Gate
Timer1 gate source is software configurable to be the T1G pin or the output of Comparator C2. This allows the device to directly time external events using T1G or analog events using Comparator C2. See the CMCON1 register (Register 8-2) for selecting the Timer1 gate source. This feature can simplify the software for a Delta-Sigma A/D converter and many other applications. For more information on Delta-Sigma A/D converters, see the Microchip web site (www.microchip.com). Note: TMR1GE bit of the T1CON register must be set to use the Timer1 gate.
Timer1 gate can be inverted using the T1GINV bit of the T1CON register, whether it originates from the T1G pin or Comparator C2 output. This configures Timer1 to measure either the active-high or active-low time between events.
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6.7 Timer1 Interrupt 6.8 Timer1 Operation During Sleep
The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: * Timer1 interrupt enable bit of the PIE1 register * PEIE bit of the INTCON register * GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: The TMR1H:TMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts. Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: * TMR1ON bit of the T1CON register must be set * TMR1IE bit of the PIE1 register must be set * PEIE bit of the INTCON register must be set The device will wake-up on an overflow and execute the next instruction. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine (0004h).
6.9
Clock Source for LCD Module
The Timer1 oscillator can be used to provide a clock for the LCD module. This clock may be configured to remain running during Sleep. For more information, see Section 10.0 "Liquid Crystal Display (LCD) Driver Module".
FIGURE 6-2:
T1CKI = 1 when TMR1 Enabled
TIMER1 INCREMENTING EDGE
T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
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6.10 Timer1 Control Register
The Timer1 Control register (T1CON), shown in Register 6-1, is used to control Timer1 and select the various features of the Timer1 module.
REGISTER 6-1:
R/W-0 T1GINV bit 7 Legend: R = Readable bit -n = Value at POR bit 7
(1)
T1CON: TIMER 1 CONTROL REGISTER
R/W-0 R/W-0
(2)
R/W-0 T1CKPS0
R/W-0 T1OSCEN
R/W-0 T1SYNC
R/W-0 TMR1CS
R/W-0 TMR1ON bit 0
TMR1GE
T1CKPS1
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
T1GINV: Timer1 Gate Invert bit(1) 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) TMR1GE: Timer1 Gate Enable bit(2) If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 Gate function 0 = Timer1 is always counting T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value T1OSCEN: LP Oscillator Enable Control bit If INTOSC without CLKOUT oscillator is active: 1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off Else: This bit is ignored. LP oscillator is disabled. T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from T1CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 T1GINV bit inverts the Timer1 gate logic, regardless of source. TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CMCON1 register, as a Timer1 gate source.
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
Note 1: 2:
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TABLE 6-1:
Name
CMCON1 INTCON PIE1 PIR1 TMR1H TMR1L T1CON Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Bit 6
-- PEIE ADIE ADIF
Bit 7
-- GIE EEIE EEIF
Bit 5
-- T0IE RCIE RCIF
Bit 4
-- INTE TXIE TXIF
Bit 3
-- RBIE SSPIE SSPIF
Bit 2
-- T0IF CCP1IE CCP1IF
Bit 1
T1GSS INTF TMR2IE TMR2IF
Bit 0
C2SYNC RBIF TMR1IE TMR1IF
Value on POR, BOR
---- --10 0000 000x 0000 0000 0000 0000 xxxx xxxx xxxx xxxx
Value on all other Resets
---- --10 0000 000x 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
0000 0000
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module.
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7.0 TIMER2 MODULE
The Timer2 module is an 8-bit timer with the following features: * * * * * 8-bit timer register (TMR2) 8-bit period register (PR2) Interrupt on TMR2 match with PR2 Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a `1'. Timer2 is turned off by clearing the TMR2ON bit to a `0'. The Timer2 prescaler is controlled by the T2CKPS bits in the T2CON register. The Timer2 postscaler is controlled by the TOUTPS bits in the T2CON register. The prescaler and postscaler counters are cleared when: * A write to TMR2 occurs. * A write to T2CON occurs. * Any device Reset occurs (Power-on Reset, MCLR Reset, Watchdog Timer Reset, or Brown-out Reset). Note: TMR2 is not cleared when T2CON is written.
See Figure 7-1 for a block diagram of Timer2.
7.1
Timer2 Operation
The clock input to the Timer2 module is the system instruction clock (FOSC/4). The clock is fed into the Timer2 prescaler, which has prescale options of 1:1, 1:4 or 1:16. The output of the prescaler is then used to increment the TMR2 register. The values of TMR2 and PR2 are constantly compared to determine when they match. TMR2 will increment from 00h until it matches the value in PR2. When a match occurs, two things happen: * TMR2 is reset to 00h on the next increment cycle. * The Timer2 postscaler is incremented. The match output of the Timer2/PR2 comparator is then fed into the Timer2 postscaler. The postscaler has postscale options of 1:1 to 1:16 inclusive. The output of the Timer2 postscaler is used to set the TMR2IF interrupt flag bit in the PIR1 register.
FIGURE 7-1:
TIMER2 BLOCK DIAGRAM
TMR2 Output Sets Flag bit TMR2IF
FOSC/4
Prescaler 1:1, 1:4, 1:16 2 T2CKPS<1:0>
TMR2 Comparator
Reset Postscaler 1:1 to 1:16 4 TOUTPS<3:0>
EQ
PR2
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REGISTER 7-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
T2CON: TIMER 2 CONTROL REGISTER
R/W-0 R/W-0 TOUTPS2 R/W-0 TOUTPS1 R/W-0 TOUTPS0 R/W-0 TMR2ON R/W-0 T2CKPS1 R/W-0 T2CKPS0 bit 0
TOUTPS3
Unimplemented: Read as `0' TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 = 1:4 Postscaler 0100 = 1:5 Postscaler 0101 = 1:6 Postscaler 0110 = 1:7 Postscaler 0111 = 1:8 Postscaler 1000 = 1:9 Postscaler 1001 = 1:10 Postscaler 1010 = 1:11 Postscaler 1011 = 1:12 Postscaler 1100 = 1:13 Postscaler 1101 = 1:14 Postscaler 1110 = 1:15 Postscaler 1111 = 1:16 Postscaler TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16
bit 2
bit 1-0
TABLE 7-1:
Name INTCON PIE1 PIR1 PR2 TMR2 T2CON Legend: Bit 7 GIE EEIE EEIF
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Bit 6 PEIE ADIE ADIF Bit 5 T0IE RCIE RCIF Bit 4 INTE TXIE TXIF Bit 3 RBIE SSPIE SSPIF Bit 2 T0IF CCP1IE CCP1IF Bit 1 INTF TMR2IE TMR2IF Bit 0 RBIF TMR1IE TMR1IF Value on POR, BOR 0000 000x 0000 0000 0000 0000 1111 1111 0000 0000 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 TOUTPS1 Value on all other Resets 0000 000x 0000 0000 0000 0000 1111 1111 0000 0000 -000 0000
Timer2 Module Period Register Holding Register for the 8-bit TMR2 Register -- TOUTPS3 TOUTPS2
x = unknown, u = unchanged, - = unimplemented read as `0'. Shaded cells are not used for Timer2 module.
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8.0 COMPARATOR MODULE
8.1 Comparator Overview
Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. The comparators are very useful mixed signal building blocks because they provide analog functionality independent of the program execution. The Analog Comparator module includes the following features: * Dual comparators * Multiple comparator configurations * Comparator outputs are available internally/externally * Programmable output polarity * Interrupt-on-change * Wake-up from Sleep * Timer1 gate (count enable) * Output synchronization to Timer1 clock input * Programmable voltage reference Note: Only Comparator C2 can be linked to Timer1. Output A comparator is shown in Figure 8-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level.
FIGURE 8-1:
VIN+ VIN-
SINGLE COMPARATOR
+ - Output
VINVIN+
Note:
The black areas of the output of the comparator represents the uncertainty due to input offsets and response time.
This device contains two comparators as shown in Figure 8-2 and Figure 8-3. The comparators are not independently configurable.
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FIGURE 8-2: COMPARATOR C1 OUTPUT BLOCK DIAGRAM
C1INV C1
MULTIPLEX Note 1: 2: MULTIPLEX Note 1: 2: 3:
To C1OUT pin
FIGURE 8-3:
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Port Pins Port Pins
D Q1 EN
Q RD CMCON0
To Data Bus
Set C1IF bit D Q3*RD CMCON0 EN Q
CL
Reset Q1 and Q3 are phases of the four-phase system clock (FOSC). Q1 is held high during Sleep mode.
COMPARATOR C2 OUTPUT BLOCK DIAGRAM
C2SYNC C2INV C2 D Timer1 clock source(1) Q 0 1
To SYNCC2OUT To C2OUT pin
D Q1 EN
Q RD CMCON0
To Data Bus
Set C2IF bit D Q3*RD CMCON0 EN Q
CL
Reset Comparator output is latched on falling edge of Timer1 clock source. Q1 and Q3 are phases of the four-phase system clock (FOSC). Q1 is held high during Sleep mode.
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8.1.1 ANALOG INPUT CONNECTION CONSIDERATIONS
A simplified circuit for an analog input is shown in Figure 8-4. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. Note 1: When reading a PORT register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified.
FIGURE 8-4:
ANALOG INPUT MODEL
VDD
Rs < 10K AIN VA CPIN 5 pF
VT 0.6V
RIC To Comparator
VT 0.6V
ILEAKAGE 500 nA
Vss Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Source Impedance RS VA = Analog Voltage = Threshold Voltage VT
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8.2 Comparator Configuration
There are eight modes of operation for the comparator. The CM<2:0> bits of the CMCON0 register are used to select these modes as shown in Figure 8-5. I/O lines change as a function of the mode and are designated as follows: * Analog function (A): digital input buffer is disabled * Digital function (D): comparator digital output, overrides port function * Normal port function (I/O): independent of comparator The port pins denoted as "A" will read as a `0' regardless of the state of the I/O pin or the I/O control TRIS bit. Pins used as analog inputs should also have the corresponding TRIS bit set to `1' to disable the digital output driver. Pins denoted as "D" should have the corresponding TRIS bit set to `0' to enable the digital output driver. Note: Comparator interrupts should be disabled during a Comparator mode change to prevent unintended interrupts.
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FIGURE 8-5: COMPARATOR I/O OPERATING MODES
Two Independent Comparators CM<2:0> = 100 VINC1IN- A
C1IN+ C2INC2 Off (Read as `0') C2IN+
A A A
Comparators Reset (POR Default Value) CM<2:0> = 000 A VINC1INC1IN+ A C2INA
VIN+ VINVIN+
C1
Off (Read as `0')
VIN+ VINVIN+
C1
C1OUT
C2IN+ A
C2
C2OUT
Three Inputs Multiplexed to Two Comparators CM<2:0> = 001
C1INC1IN+
A A
CIS = 0 CIS = 1
VINVIN+ VINVIN+
C2 C2OUT C1 C1OUT
One Independent Comparator with Reference Option CM<2:0> = 101 VINI/O
C1INC1IN+ C2INC2IN+
I/O
VIN+ C1 VINCIS = 0 VIN+ C2
Off (Read as `0')
C2INC2IN+
A A
A A
C2OUT C2OUT(pin)
Internal CIS = 1 Fixed Voltage Ref
Four Inputs Multiplexed to Two Comparators CM<2:0> = 010
C1INC1IN+ C2INC2IN+
A A
CIS = 0 CIS = 1
VINVIN+ VINVIN+
C2 C2OUT C1 C1OUT
Two Common Reference Comparators with Outputs CM<2:0> = 110 A VINC1INVIN+
C1OUT(pin)
D A A D
C1
C1OUT
A A
CIS = 0 CIS = 1
C2INC2IN+ C2OUT(pin)
VINVIN+
C2 C2OUT
From CVREF Module
Two Common Reference Comparators CM<2:0> = 011 A VINC1INC1IN+
I/O
VIN+
C1
C1OUT
Comparators Off (Lowest Power) CM<2:0> = 111 I/O VINC1INC1IN+
I/O
VIN+
C1
Off (Read as `0')
C2INC2IN+
A A
VINVIN+
C2 C2OUT
C2INC2IN+
I/O I/O
VINVIN+
C2 Off (Read as `0')
Legend: A = Analog Input, ports always reads `0' I/O = Normal port I/O
CIS = Comparator Input Switch (CMCON0<3>) D = Comparator Digital Output
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8.3 Comparator Control 8.4 Comparator Response Time
The CMCON0 register (Register 8-1) provides access to the following comparator features: * * * * Mode selection Output state Output polarity Input switch The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference Specifications in Section 19.0 "Electrical Specifications" for more details.
8.3.1
COMPARATOR OUTPUT STATE
Each comparator state can always be read internally via the associated CxOUT bit of the CMCON0 register. The comparator outputs are directed to the CxOUT pins when CM<2:0> = 110. When this mode is selected, the TRIS bits for the associated CxOUT pins must be cleared to enable the output drivers.
8.5
Comparator Interrupt Operation
8.3.2
COMPARATOR OUTPUT POLARITY
Inverting the output of a comparator is functionally equivalent to swapping the comparator inputs. The polarity of a comparator output can be inverted by setting the CxINV bits of the CMCON0 register. Clearing CxINV results in a non-inverted output. A complete table showing the output state versus input conditions and the polarity bit is shown in Table 8-1.
TABLE 8-1:
OUTPUT STATE VS. INPUT CONDITIONS
CxINV 0 0 1 1 CxOUT 0 1 1 0
Input Conditions VIN- > VIN+ VIN- < VIN+ VIN- > VIN+ VIN- < VIN+ Note:
The comparator interrupt flag is set whenever there is a change in the output value of the comparator. Changes are recognized by means of a mismatch circuit which consists of two latches and an exclusive-or gate (see Figure 8-2 and Figure 8-3). One latch is updated with the comparator output level when the CMCON0 register is read. This latch retains the value until the next read of the CMCON0 register or the occurrence of a Reset. The other latch of the mismatch circuit is updated on every Q1 system clock. A mismatch condition will occur when a comparator output change is clocked through the second latch on the Q1 clock cycle. The mismatch condition will persist, holding the CxIF bit of the PIR2 register true, until either the CMCON0 register is read or the comparator output returns to the previous state. Note: A write operation to the CMCON0 register will also clear the mismatch condition because all writes include a read operation at the beginning of the write cycle.
CxOUT refers to both the register bit and output pin.
Software will need to maintain information about the status of the comparator output to determine the actual change that has occurred. The CxIF bit of the PIR2 register is the comparator interrupt flag. This bit must be reset in software by clearing it to `0'. Since it is also possible to write a `1' to this register, a simulated interrupt may be initiated. The CxIE bit of the PIE2 register and the PEIE and GIE bits of the INTCON register must all be set to enable comparator interrupts. If any of these bits are cleared, the interrupt is not enabled, although the CxIF bit of the PIR2 register will still be set if an interrupt condition occurs. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of CMCON0. This will end the mismatch condition. See Figures 8-6 and 8-7 Clear the CxIF interrupt flag.
8.3.3
COMPARATOR INPUT SWITCH
The inverting input of the comparators may be switched between two analog pins or an analog input pin and and the fixed voltage reference in the following modes: * CM<2:0> = 001 (Comparator C1 only) * CM<2:0> = 010 (Comparators C1 and C2) * CM<2:0> = 101 (Comparator C2 only) In the above modes, both pins remain in Analog mode regardless of which pin is selected as the input. The CIS bit of the CMCON0 register controls the comparator input switch.
A persistent mismatch condition will preclude clearing the CxIF interrupt flag. Reading CMCON0 will end the mismatch condition and allow the CxIF bit to be cleared.
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FIGURE 8-6: COMPARATOR INTERRUPT TIMING W/O CMCON0 READ
8.6
Operation During Sleep
Q1 Q3 CIN+ COUT Set CxIF (level) CxIF reset by software TRT
The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in the Section 19.0 "Electrical Specifications". If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. The comparator is turned off by selecting mode CM<2:0> = 000 or CM<2:0> = 111 of the CMCON0 register. A change to the comparator output can wake-up the device from Sleep. To enable the comparator to wake the device from Sleep, the CxIE bit of the PIE2 register and the PEIE bit of the INTCON register must be set. The instruction following the Sleep instruction always executes following a wake from Sleep. If the GIE bit of the INTCON register is also set, the device will then execute the Interrupt Service Routine.
FIGURE 8-7:
COMPARATOR INTERRUPT TIMING WITH CMCON0 READ
Q1 Q3 CIN+ COUT Set CxIF (level) CxIF cleared by CMCON0 read reset by software TRT
8.7
Effects of a Reset
Note 1: If a change in the CMCON0 register (CxOUT) occurs when a read operation is being executed (start of the Q2 cycle), then the CxIF Interrupt Flag bit of the PIR2 register may not get set. 2: When either comparator is first enabled, bias circuitry in the Comparator module may cause an invalid output from the comparator until the bias circuitry is stable. Allow about 1 s for bias settling then clear the mismatch condition and interrupt flags before enabling comparator interrupts.
A device Reset forces the CMCON0 and CMCON1 registers to their Reset states. This forces the Comparator module to be in the Comparator Reset mode (CM<2:0> = 000). Thus, all comparator inputs are analog inputs with the comparator disabled to consume the smallest current possible.
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REGISTER 8-1:
R-0 C2OUT bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
CMCON0: COMPARATOR CONFIGURATION REGISTER
R-0 C1OUT R/W-0 C2INV R/W-0 C1INV R/W-0 CIS R/W-0 CM2 R/W-0 CM1 R/W-0 CM0 bit 0
C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1: 1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VINC1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1: 1 = C1 VIN+ < C1 VIN0 = C1 VIN+ > C1 VINC2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted C1INV: Comparator 1 Output Inversion bit 1 = C1 Output inverted 0 = C1 Output not inverted CIS: Comparator Input Switch bit When CM<2:0> = 010: 1 = C1IN+ connects to C1 VINC2IN+ connects to C2 VIN0 = C1IN- connects to C1 VINC2IN- connects to C2 VINWhen CM<2:0> = 001: 1 = C1IN+ connects to C1 VIN0 = C1IN- connects to C1 VINWhen CM<2:0> = 101: (16F91x/946) 1 = C2 VIN+ connects to fixed voltage reference 0 = C2 VIN+ connects to C2IN+ CM<2:0>: Comparator Mode bits (See Figure 8-5) 000 = Comparators off. CxIN pins are configured as analog 001 = Three inputs multiplexed to two comparators 010 = Four inputs multiplexed to two comparators 011 = Two common reference comparators 100 = Two independent comparators 101 = One independent comparator 110 = Two comparators with outputs and common reference 111 = Comparators off. CxIN pins are configured as digital I/O
bit 6
bit 5
bit 4
bit 3
bit 2-0
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8.8 Comparator C2 Gating Timer1 8.9
This feature can be used to time the duration or interval of analog events. Clearing the T1GSS bit of the CMCON1 register will enable Timer1 to increment based on the output of Comparator C2. This requires that Timer1 is on and gating is enabled. See Section 6.0 "Timer1 Module with Gate Control" for details. It is recommended to synchronize Comparator C2 with Timer1 by setting the C2SYNC bit when the comparator is used as the Timer1 gate source. This ensures Timer1 does not miss an increment if the comparator changes during an increment.
Synchronizing Comparator C2 Output to Timer1
The output of Comparator C2 can be synchronized with Timer1 by setting the C2SYNC bit of the CMCON1 register. When enabled, the comparator output is latched on the falling edge of the Timer1 clock source. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. Reference the comparator block diagrams (Figure 8-2 and Figure 8-3) and the Timer1 Block Diagram (Figure 6-1) for more information.
REGISTER 8-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-2 bit 1
CMCON1: COMPARATOR CONFIGURATION REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 T1GSS R/W-0 C2SYNC bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' T1GSS: Timer1 Gate Source Select bit(1) 1 = Timer1 gate source is T1G pin (pin should be configured as digital input) 0 = Timer1 gate source is Comparator C2 output C2SYNC: Comparator C2 Output Synchronization bit(2) 1 = Output is synchronized with falling edge of Timer1 clock 0 = Output is asynchronous Refer to Section 6.6 "Timer1 Gate". Refer to Figure 8-3.
bit 0
Note 1: 2:
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8.10 Comparator Voltage Reference
EQUATION 8-1: CVREF OUTPUT VOLTAGE
The Comparator Voltage Reference module provides an internally generated voltage reference for the comparators. The following features are available: * * * * Independent from Comparator operation Two 16-level voltage ranges Output clamped to VSS Ratiometric with VDD VRR = 1 (low range): CVREF = (VR<3:0>/24) x VDD VRR = 0 (high range): CVREF = (VDD/4) + (VR<3:0> x VDD/32) The full range of VSS to VDD cannot be realized due to the construction of the module. See Figure 8-8.
The VRCON register (Register 8-3) controls the Voltage Reference module shown in Figure 8-8.
8.10.3
OUTPUT CLAMPED TO VSS
8.10.1
INDEPENDENT OPERATION
The CVREF output voltage can be set to Vss with no power consumption by configuring VRCON as follows: * VREN = 0 * VRR = 1 * VR<3:0> = 0000 This allows the comparator to detect a zero-crossing while not consuming additional CVREF module current.
The comparator voltage reference is independent of the comparator configuration. Setting the VREN bit of the VRCON register will enable the voltage reference.
8.10.2
OUTPUT VOLTAGE SELECTION
The CVREF voltage reference has 2 ranges with 16 voltage levels in each range. Range selection is controlled by the VRR bit of the VRCON register. The 16 levels are set with the VR<3:0> bits of the VRCON register.
8.10.4
OUTPUT RATIOMETRIC TO VDD
The CVREF output voltage is determined by the following
equations:
The comparator voltage reference is VDD derived and therefore, the CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the Comparator Voltage Reference can be found in Section 19.0 "Electrical Specifications".
REGISTER 8-3:
R/W-0 VREN bit 7 Legend: R = Readable bit -n = Value at POR bit 7
VRCON: VOLTAGE REFERENCE CONTROL REGISTER
U-0 -- R/W-0 VRR U-0 -- R/W-0 VR3 R/W-0 VR2 R/W-0 VR1 R/W-0 VR0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
VREN: CVREF Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down, no IDD drain and CVREF = VSS. Unimplemented: Read as `0' VRR: CVREF Range Selection bit 1 = Low range 0 = High range Unimplemented: Read as `0' VR<3:0>: CVREF Value Selection bits (0 VR<3:0> 15) When VRR = 1: CVREF = (VR<3:0>/24) * VDD When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD
bit 6 bit 5
bit 4 bit 3-0
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FIGURE 8-8: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages 8R VDD 8R 16-1 Analog MUX VREN CVREF to Comparator Input
15 14 2 1 0
R
R
R
R
VRR
VR<3:0>(1) VREN VR<3:0> = 0000 VRR Note 1: Care should be taken to ensure VREF remains within the comparator common mode input range. See Section 19.0 "Electrical Specifications" for more detail.
TABLE 8-2:
SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES
Bit 7 ANS7 C2OUT -- GIE OSFIE OSFIF RA7 TRISA7 VREN Bit 6 ANS6 C1OUT -- PEIE C2IE C2IF RA6 TRISA6 -- Bit 5 ANS5 C2INV -- T0IE C1IE C1IF RA5 VRR Bit 4 ANS4 C1INV -- INTE LCDIE LCDIF RA4 -- Bit 3 ANS3 CIS -- RBIE -- -- RA3 VR3 Bit 2 ANS2 CM2 -- T0IF LVDIE LVDIF RA2 VR2 Bit 1 ANS1 CM1 T1GSS INTF -- -- RA1 TRISA1 VR1 Bit 0 ANS0 CM0 C2SYNC RBIF CCP2IE CCP2IF RA0 TRISA0 VR0 Value on POR, BOR 1111 1111 0000 0000 ---- --10 0000 000x 0000 -0-0 0000 -0-0 xxxx xxxx 1111 1111 0-0- 0000 Value on all other Resets 1111 1111 0000 0000 ---- --10 0000 000x 0000 -0-0 0000 -0-0 uuuu uuuu 1111 1111 0000 0000
Name ANSEL CMCON0 CMCON1 INTCON PIE2 PIR2 PORTA TRISA VRCON Legend:
TRISA5 TRISA4 TRISA3 TRISA2
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used for comparator.
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NOTES:
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9.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (AUSART)
The AUSART module includes the following capabilities: * * * * * * * * * * Full-duplex asynchronous transmit and receive Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Address detection in 9-bit mode Input buffer overrun error detection Received character framing error detection Half-duplex synchronous master Half-duplex synchronous slave Sleep operation
The Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The AUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device.
Block diagrams of the AUSART transmitter and receiver are shown in Figure 9-1 and Figure 9-2.
FIGURE 9-1:
AUSART TRANSMIT BLOCK DIAGRAM
Data Bus TXIE TXIF LSb Interrupt
TXREG Register 8 MSb (8)
TX/CK pin Pin Buffer and Control
***
Transmit Shift Register (TSR)
0
TXEN Baud Rate Generator TRMT FOSC /n n +1 SPBRG Multiplier SYNC BRGH x4 1 x x16 x64 0 1 0 0 TX9D TX9 SPEN
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FIGURE 9-2: AUSART RECEIVE BLOCK DIAGRAM
SPEN CREN OERR
RX/DT pin Pin Buffer and Control Baud Rate Generator FOSC Data Recovery
MSb Stop (8) 7
RSR Register
LSb 0 START
***
RX9
1
/n
+1 SPBRG
Multiplier SYNC BRGH
x4 1 x
x16 x64 0 1 0 0
n FIFO
FERR
RX9D
RCREG Register 8
Data Bus RCIF RCIE Interrupt
The operation of the AUSART module is controlled through two registers: * Transmit Status and Control (TXSTA) * Receive Status and Control (RCSTA) These registers are detailed in Register 9-1 and Register 9-2 respectively.
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9.1 AUSART Asynchronous Mode
Note 1: When the SPEN bit is set the RX/DT I/O pin is automatically configured as an input, regardless of the state of the corresponding TRIS bit and whether or not the AUSART receiver is enabled. The RX/DT pin data can be read via a normal PORT read but PORT latch data output is precluded. 2: The TXIF transmitter interrupt flag is set when the TXEN enable bit is set. The AUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a `1' data bit, and a VOL space state which represents a `0' data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the mark state. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data format is 8 bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table 9-5 for examples of baud rate configurations. The AUSART transmits and receives the LSb first. The AUSART's transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit.
9.1.1.2
Transmitting Data
9.1.1
AUSART ASYNCHRONOUS TRANSMITTER
A transmission is initiated by writing a character to the TXREG register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the TXREG until the Stop bit of the previous character has been transmitted. The pending character in the TXREG is then transferred to the TSR in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXREG.
9.1.1.3
Transmit Interrupt Flag
The AUSART transmitter block diagram is shown in Figure 9-1. The heart of the transmitter is the serial Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the TXREG register.
9.1.1.1
Enabling the Transmitter
The AUSART transmitter is enabled for asynchronous operations by configuring the following three control bits: * TXEN = 1 * SYNC = 0 * SPEN = 1 All other AUSART control bits are assumed to be in their default state. Setting the TXEN bit of the TXSTA register enables the transmitter circuitry of the AUSART. Clearing the SYNC bit of the TXSTA register configures the AUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the AUSART and automatically configures the TX/CK I/O pin as an output. The LCD SEG9 function must be disabled by clearing the SE9 bit of the LCDSE1 register, if the TX/CK pin is shared with the LCD peripheral.
The TXIF interrupt flag bit of the PIR1 register is set whenever the AUSART transmitter is enabled and no character is being held for transmission in the TXREG. In other words, the TXIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the TXREG. The TXIF flag bit is not cleared immediately upon writing TXREG. TXIF becomes valid in the second instruction cycle following the write execution. Polling TXIF immediately following the TXREG write will return invalid results. The TXIF bit is read-only, it cannot be set or cleared by software. The TXIF interrupt can be enabled by setting the TXIE interrupt enable bit of the PIE1 register. However, the TXIF flag bit will be set whenever the TXREG is empty, regardless of the state of TXIE enable bit. To use interrupts when transmitting data, set the TXIE bit only when there is more data to send. Clear the TXIE interrupt enable bit upon writing the last character of the transmission to the TXREG.
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9.1.1.4 TSR Status 9.1.1.6
1.
Asynchronous Transmission Set-up:
The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: The TSR register is not mapped in data memory, so it is not available to the user.
2. 3.
4.
9.1.1.5
Transmitting 9-Bit Characters
5.
The AUSART supports 9-bit character transmissions. When the TX9 bit of the TXSTA register is set the AUSART will shift 9 bits out for each character transmitted. The TX9D bit of the TXSTA register is the ninth, and Most Significant, data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the 8 Least Significant bits into the TXREG. All nine bits of data will be transferred to the TSR shift register immediately after the TXREG is written. A special 9-bit Address mode is available for use with multiple receivers. See Section 9.1.2.7 "Address Detection" for more information on the Address mode.
6. 7.
Initialize the SPBRG register and the BRGH bit to achieve the desired baud rate (see Section 9.2 "AUSART Baud Rate Generator (BRG)"). Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the 8 Least Significant data bits are an address when the receiver is set for address detection. Enable the transmission by setting the TXEN control bit. This will cause the TXIF interrupt bit to be set. If interrupts are desired, set the TXIE interrupt enable bit of the PIE1 register. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are also set. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. Load 8-bit data into the TXREG register. This will start the transmission.
FIGURE 9-3:
Write to TXREG BRG Output (Shift Clock) TX/CK pin TXIF bit (Transmit Buffer Empty Flag)
ASYNCHRONOUS TRANSMISSION
Word 1
Start bit 1 TCY
bit 0
bit 1 Word 1
bit 7/8
Stop bit
TRMT bit (Transmit Shift Reg. Empty Flag)
Word 1 Transmit Shift Reg
FIGURE 9-4:
Write to TXREG BRG Output (Shift Clock) TX/CK pin TXIF bit (Transmit Buffer Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag)
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Word 1 Word 2
Start bit 1 TCY
bit 0
bit 1 Word 1
bit 7/8
Stop bit
Start bit Word 2
bit 0
1 TCY Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg.
Note:
This timing diagram shows two consecutive transmissions.
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TABLE 9-1:
Name INTCON LCDCON LCDSE1 PIE1 PIR1 RCSTA SPBRG SSPCON TRISC TXREG TXSTA Legend:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7 GIE Bit 6 PEIE SLPEN SE14 ADIE ADIF RX9 BRG6 SSPOV TRISC6 TX9 Bit 5 T0IE WERR SE13 RCIE RCIF SREN BRG5 SSPEN TRISC5 TXEN Bit 4 INTE VLCDEN SE12 TXIE TXIF CREN BRG4 CKP TRISC4 SYNC Bit 3 RBIE CS1 SE11 SSPIE SSPIF ADDEN BRG3 SSPM3 TRISC3 -- Bit 2 T0IF CS0 SE10 CCP1IE CCP1IF FERR BRG2 SSPM2 TRISC2 BRGH Bit 1 INTF LMUX1 SE9 TMR2IE TMR2IF OERR BRG1 SSPM1 TRISC1 TRMT Bit 0 RBIF LMUX0 SE8 TMR1IE TMR1IF RX9D BRG0 SSPM0 TRISC0 TX9D Value on POR, BOR 0000 000x 0001 0011 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 0000 0000 1111 1111 0000 0000 0000 -010 Value on all other Resets 0000 000x 0001 0011 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 0000 0000 1111 1111 0000 0000 0000 -010
LCDEN SE15 EEIE EEIF SPEN BRG7 WCOL TRISC7 CSRC
AUSART Transmit Data Register
x = unknown, - = unimplemented read as `0'. Shaded cells are not used for Asynchronous Transmission.
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9.1.2 AUSART ASYNCHRONOUS RECEIVER 9.1.2.2 Receiving Data
The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 9-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate. When all 8 or 9 bits of the character have been shifted in, they are immediately transferred to a two character First-In First-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the AUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCREG register. The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting `0' or `1' is shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is always a `1'. If the data recovery circuit samples a `0' in the Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. See Section 9.1.2.4 "Receive Framing Error" for more information on framing errors. Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the AUSART receive FIFO and the RCIF interrupt flag bit of the PIR1 register is set. The top character in the FIFO is transferred out of the FIFO by reading the RCREG register. Note: If the receive FIFO is overrun, no additional characters will be received until the overrun condition is cleared. See Section 9.1.2.5 "Receive Overrun Error" for more information on overrun errors.
9.1.2.1
Enabling the Receiver
The AUSART receiver is enabled for asynchronous operation by configuring the following three control bits: * CREN = 1 * SYNC = 0 * SPEN = 1 All other AUSART control bits are assumed to be in their default state. Setting the CREN bit of the RCSTA register enables the receiver circuitry of the AUSART. Clearing the SYNC bit of the TXSTA register configures the AUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the AUSART and automatically configures the RX/DT I/O pin as an input. The LCD SEG8 function must be disabled by clearing the SE8 bit of the LCDSE1 register, if the RX/DT pin is shared with the LCD peripheral. Note: When the SPEN bit is set the TX/CK I/O pin is automatically configured as an output, regardless of the state of the corresponding TRIS bit and whether or not the AUSART transmitter is enabled. The PORT latch is disconnected from the output driver so it is not possible to use the TX/CK pin as a general purpose output.
9.1.2.3
Receive Interrupts
The RCIF interrupt flag bit of the PIR1 register is set whenever the AUSART receiver is enabled and there is an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCIF interrupts are enabled by setting all of the following bits: * RCIE interrupt enable bit of the PIE1 register * PEIE peripheral interrupt enable bit of the INTCON register * GIE global interrupt enable bit of the INTCON register The RCIF interrupt flag bit of the PIR1 register will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits.
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9.1.2.4 Receive Framing Error 9.1.2.7 Address Detection
Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG. The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. The FERR bit can be forced clear by clearing the SPEN bit of the RCSTA register which resets the AUSART. Clearing the CREN bit of the RCSTA register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Note: If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREG will not clear the FERR bit. A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCSTA register. Address detection requires 9-bit character reception. When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCIF interrupt bit of the PIR1 register. All other characters will be ignored. Upon receiving an address character, user software determines if the address matches its own. Upon address match, user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user software detects the end of the message, determined by the message protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN bit.
9.1.2.5
Receive Overrun Error
The receive FIFO buffer can hold two characters. An overrun error will be generated If a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register.
9.1.2.6
Receiving 9-bit Characters
The AUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the AUSART will shift 9 bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG.
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9.1.2.8
1.
Asynchronous Reception Set-up:
9.1.2.9
9-bit Address Detection Mode Set-up
2.
3.
4. 5. 6.
7.
8.
9.
Initialize the SPBRG register and the BRGH bit to achieve the desired baud rate (see Section 9.2 "AUSART Baud Rate Generator (BRG)"). Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit. Enable reception by setting the CREN bit. The RCIF interrupt flag bit of the PIR1 register will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE bit of the PIE1 register was also set. Read the RCSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. Get the received 8 Least Significant data bits from the receive buffer by reading the RCREG register. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit.
This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRG register and the BRGH bit to achieve the desired baud rate (see Section 9.2 "AUSART Baud Rate Generator (BRG)"). 2. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 3. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 4. Enable 9-bit reception by setting the RX9 bit. 5. Enable address detection by setting the ADDEN bit. 6. Enable reception by setting the CREN bit. 7. The RCIF interrupt flag bit of the PIR1 register will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit of the PIE1 register was also set. 8. Read the RCSTA register to get the error flags. The ninth data bit will always be set. 9. Get the received 8 Least Significant data bits from the receive buffer by reading the RCREG register. Software determines if this is the device's address. 10. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts.
FIGURE 9-5:
RX/DT pin Rcv Shift Reg Rcv Buffer Reg Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN
ASYNCHRONOUS RECEPTION
Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 bit 7/8 Stop bit Start bit bit 7/8 Stop bit
Word 1 RCREG
Word 2 RCREG
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.
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TABLE 9-2:
Name INTCON LCDCON LCDSE1 PIE1 PIR1 RCREG RCSTA SPBRG SSPCON TRISC TXSTA Legend:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7 GIE Bit 6 PEIE SLPEN SE14 ADIE ADIF RX9 BRG6 SSPOV TRISC6 TX9 Bit 5 T0IE WERR SE13 RCIE RCIF SREN BRG5 SSPEN TRISC5 TXEN Bit 4 INTE VLCDEN SE12 TXIE TXIF CREN BRG4 CKP TRISC4 SYNC Bit 3 RBIE CS1 SE11 SSPIE SSPIF ADDEN BRG3 SSPM3 TRISC3 -- Bit 2 T0IF CS0 SE10 CCP1IE CCP1IF FERR BRG2 SSPM2 TRISC2 BRGH Bit 1 INTF LMUX1 SE9 TMR2IE TMR2IF OERR BRG1 SSPM1 TRISC1 TRMT Bit 0 RBIF LMUX0 SE8 TMR1IE TMR1IF RX9D BRG0 SSPM0 TRISC0 TX9D Value on POR, BOR 0000 000x 0001 0011 0000 0000 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 0000 0000 1111 1111 0000 -010 Value on all other Resets 0000 000x 0001 0011 0000 0000 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 0000 0000 1111 1111 0000 -010
LCDEN SE15 EEIE EEIF SPEN BRG7 WCOL TRISC7 CSRC
AUSART Receive Data Register
x = unknown, - = unimplemented read as `0'. Shaded cells are not used for Asynchronous Reception.
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REGISTER 9-1:
R/W-0 CSRC bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 TX9 R/W-0 TXEN(1) R/W-0 SYNC U-0 -- R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit 0
CSRC: Clock Source Select bit Asynchronous mode: Don't care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled SYNC: AUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode Unimplemented: Read as `0' BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. SREN/CREN overrides TXEN in Sync mode.
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1
bit 0 Note 1:
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REGISTER 9-2:
R/W-0 SPEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1)
R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0
SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don't care Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave Don't care CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don't care Synchronous mode: Must be set to `0' FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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9.2 AUSART Baud Rate Generator (BRG)
EXAMPLE 9-1: CALCULATING BAUD RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode:
FOSC Desired Baud Rate = -------------------------------------64 ( SPBRG + 1 )
The Baud Rate Generator (BRG) is an 8-bit timer that is dedicated to the support of both the asynchronous and synchronous AUSART operation. The SPBRG register determines the period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by the BRGH bit of the TXSTA register. In Synchronous mode, the BRGH bit is ignored. Table 9-3 contains the formulas for determining the baud rate. Example 9-1 provides a sample calculation for determining the baud rate and baud rate error. Typical baud rates and error values for various asynchronous modes have been computed for your convenience and are shown in Table 9-3. It may be advantageous to use the high baud rate (BRGH = 1), to reduce the baud rate error. Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate.
Solving for SPBRG:
FOSC -------------------------------------------Desired Baud Rate X = --------------------------------------------- - 1 64 16000000 ----------------------9600 = ----------------------- - 1 64 = [ 25.042 ] = 25 16000000 Calculated Baud Rate = -------------------------64 ( 25 + 1 ) = 9615 Calc. Baud Rate - Desired Baud Rate Error = ------------------------------------------------------------------------------------------Desired Baud Rate ( 9615 - 9600 ) = ---------------------------------- = 0.16% 9600
TABLE 9-3:
SYNC 0 0 1 Legend:
BAUD RATE FORMULAS
BRGH 0 1 x AUSART Mode Asynchronous Asynchronous Synchronous Baud Rate Formula FOSC/[64 (n+1)] FOSC/[16 (n+1)] FOSC/[4 (n+1)]
Configuration Bits
x = Don't care, n = value of SPBRG register
TABLE 9-4:
Name RCSTA SPBRG TXSTA Legend:
REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Bit 7 SPEN BRG7 CSRC Bit 6 RX9 BRG6 TX9 Bit 5 SREN BRG5 TXEN Bit 4 CREN BRG4 SYNC Bit 3 ADDEN BRG3 -- Bit 2 FERR BRG2 BRGH Bit 1 OERR BRG1 TRMT Bit 0 RX9D BRG0 TX9D Value on POR, BOR 0000 000x 0000 0000 0000 -010 Value on all other Resets 0000 000x 0000 0000 0000 -010
x = unknown, - = unimplemented read as `0'. Shaded cells are not used for the Baud Rate Generator.
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TABLE 9-5:
BAUD RATE
BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0 FOSC = 20.000 MHz FOSC = 18.432 MHz Actual Rate -- 1200 2400 9600 10286 19.20k 57.60k -- % Error -- 0.00 0.00 0.00 -1.26 0.00 0.00 -- SPBRG value (decimal) -- 239 119 29 27 14 7 -- FOSC = 11.0592 MHz Actual Rate -- 1200 2400 9600 10165 19.20k 57.60k -- % Error -- 0.00 0.00 0.00 -2.42 0.00 0.00 -- SPBRG value (decimal) -- 143 71 17 16 8 2 -- FOSC = 8.000 MHz Actual Rate -- 1202 2404 9615 10417 -- -- -- % Error -- 0.16 0.16 0.16 0.00 -- -- -- SPBRG value (decimal) -- 103 51 12 11 -- -- -- SPBRG value (decimal) -- 255 129 32 29 15 -- --
Actual Rate -- 1221 2404 9470 10417 19.53k -- --
% Error -- 1.73 0.16 -1.36 0.00 1.73 -- --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
SYNC = 0, BRGH = 0 BAUD RATE FOSC = 4.000 MHz Actual Rate 300 1202 2404 -- 10417 -- -- -- % Error 0.16 0.16 0.16 -- 0.00 -- -- -- SPBRG value (decimal) 207 51 25 -- 5 -- -- -- FOSC = 3.6864 MHz Actual Rate 300 1200 2400 9600 -- 19.20k 57.60k -- % Error 0.00 0.00 0.00 0.00 -- 0.00 0.00 -- SPBRG value (decimal) 191 47 23 5 -- 2 0 -- FOSC = 2.000 MHz Actual Rate 300 1202 2404 -- 10417 -- -- -- % Error 0.16 0.16 0.16 -- 0.00 -- -- -- SPBRG value (decimal) 103 25 12 -- 2 -- -- -- FOSC = 1.000 MHz Actual Rate 300 1202 -- -- -- -- -- -- % Error 0.16 0.16 -- -- -- -- -- -- SPBRG value (decimal) 51 12 -- -- -- -- -- --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
SYNC = 0, BRGH = 1 BAUD RATE FOSC = 20.000 MHz Actual Rate -- -- -- 9615 10417 19.23k 56.82k 113.64k % Error -- -- -- 0.16 0.00 0.16 -1.36 -1.36 SPBRG value (decimal) -- -- -- 129 119 64 21 10 FOSC = 18.432 MHz Actual Rate -- -- -- 9600 10378 19.20k 57.60k 115.2k % Error -- -- -- 0.00 -0.37 0.00 0.00 0.00 SPBRG value (decimal) -- -- -- 119 110 59 19 9 FOSC = 11.0592 MHz Actual Rate -- -- -- 9600 10473 19.20k 57.60k 115.2k % Error -- -- -- 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) -- -- -- 71 65 35 11 5 FOSC = 8.000 MHz Actual Rate -- -- 2404 9615 10417 19231 55556 -- % Error -- -- 0.16 0.16 0.00 0.16 -3.55 -- SPBRG value (decimal) -- -- 207 51 47 25 8 --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
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TABLE 9-5:
BAUD RATE
BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 1 FOSC = 4.000 MHz FOSC = 3.6864 MHz Actual Rate -- 1200 2400 9600 10473 19.2k 57.60k 115.2k % Error -- 0.00 0.00 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) -- 191 95 23 21 11 3 1 FOSC = 2.000 MHz Actual Rate -- 1202 2404 9615 10417 -- -- -- % Error -- 0.16 0.16 0.16 0.00 -- -- -- SPBRG value (decimal) -- 103 51 12 11 -- -- -- FOSC = 1.000 MHz Actual Rate 300 1202 2404 -- 10417 -- -- -- % Error 0.16 0.16 0.16 -- 0.00 -- -- -- SPBRG value (decimal) 207 51 25 -- 5 -- -- -- SPBRG value (decimal) -- 207 103 25 23 12 -- --
Actual Rate -- 1202 2404 9615 10417 19.23k -- --
% Error -- 0.16 0.16 0.16 0.00 0.16 -- --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
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9.3 AUSART Synchronous Mode
9.3.1.2 Synchronous Master Transmission
Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. The AUSART can operate as either a master or slave device. Start and Stop bits are not used in synchronous transmissions. Data is transferred out of the device on the RX/DT pin. The RX/DT and TX/CK pin output drivers are automatically enabled when the AUSART is configured for synchronous master transmit operation. A transmission is initiated by writing a character to the TXREG register. If the TSR still contains all or part of a previous character the new character data is held in the TXREG until the last bit of the previous character has been transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR. The transmission of the character commences immediately following the transfer of the data to the TSR from the TXREG. Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. Note: The TSR register is not mapped in data memory, so it is not available to the user.
9.3.1
SYNCHRONOUS MASTER MODE
9.3.1.3
1.
The following bits are used to configure the AUSART for Synchronous Master operation: * * * * * SYNC = 1 CSRC = 1 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1
Synchronous Master Transmission Set-up:
2. 3. 4. 5. 6.
Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Setting the CSRC bit of the TXSTA register configures the device as a master. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the AUSART. The LCD SEG8 and SEG9 functions must be disabled by clearing the SE8 and SE9 bits of the LCDSE1 register, if the RX/DT and TX/CK pins are shared with the LCD peripheral.
7. 8.
Initialize the SPBRG register and the BRGH bit to achieve the desired baud rate (see Section 9.2 "AUSART Baud Rate Generator (BRG)"). Enable the synchronous master serial port by setting bits SYNC, SPEN, and CSRC. Disable Receive mode by clearing bits SREN and CREN. Enable Transmit mode by setting the TXEN bit. If 9-bit transmission is desired, set the TX9 bit. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. Start transmission by loading data to the TXREG register.
9.3.1.1
Master Clock
Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TX/CK line. The TX/CK pin output driver is automatically enabled when the AUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits.
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FIGURE 9-6:
RX/DT pin TX/CK pin Write to TXREG Reg TXIF bit (Interrupt Flag) TRMT bit
SYNCHRONOUS TRANSMISSION
bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7
Write Word 1
Write Word 2
TXEN bit Note:
`1' Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
`1'
FIGURE 9-7:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7
TX/CK pin Write to TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 9-6:
Name INTCON LCDCON LCDSE1 PIE1 PIR1 RCSTA SPBRG SSPCON TRISC TXREG TXSTA Legend:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Bit 7 GIE Bit 6 PEIE SLPEN SE14 ADIE ADIF RX9 BRG6 SSPOV TRISC6 TX9 Bit 5 T0IE WERR SE13 RCIE RCIF SREN BRG5 SSPEN TRISC5 TXEN Bit 4 INTE VLCDEN SE12 TXIE TXIF CREN BRG4 CKP TRISC4 SYNC Bit 3 RBIE CS1 SE11 SSPIE SSPIF ADDEN BRG3 SSPM3 TRISC3 -- Bit 2 T0IF CS0 SE10 CCP1IE CCP1IF FERR BRG2 SSPM2 TRISC2 BRGH Bit 1 INTF LMUX1 SE9 TMR2IE TMR2IF OERR BRG1 SSPM1 TRISC1 TRMT Bit 0 RBIF LMUX0 SE8 TMR1IE TMR1IF RX9D BRG0 SSPM0 TRISC0 TX9D Value on POR, BOR 0000 000x 0001 0011 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 0000 0000 1111 1111 0000 0000 0000 -010 Value on all other Resets 0000 000x 0001 0011 0000 0000 0000 0000 0000 0000 0000 000x 0000 0000 0000 0000 1111 1111 0000 0000 0000 -010
LCDEN SE15 EEIE EEIF SPEN BRG7 WCOL TRISC7 CSRC
AUSART Transmit Data Register
x = unknown, - = unimplemented read as `0'. Shaded cells are not used for Synchronous Master Transmission.
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9.3.1.4 Synchronous Master Reception 9.3.1.7 Receiving 9-bit Characters
Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the AUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register). When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the completion of the first character and CREN takes precedence. To initiate reception, set either SREN or CREN. Data is sampled at the RX/DT pin on the trailing edge of the TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR, the RCIF bit of the PIR1 register is set and the character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are available in RCREG. The RCIF bit remains set as long as there are un-read characters in the receive FIFO. The AUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the AUSART will shift 9-bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. Address detection in Synchronous modes is not supported, therefore the ADDEN bit of the RCSTA register must be cleared.
9.3.1.8
1.
Synchronous Master Reception Set-up:
9.3.1.5
Slave Clock
Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a slave receives the clock on the TX/CK line. The TX/CK pin output driver is automatically disabled when the device is configured for synchronous slave transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles should be received as there are data bits.
9.3.1.6
Receive Overrun Error
The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCREG is read to access the FIFO. When this happens the OERR bit of the RCSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCREG. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCSTA register.
Initialize the SPBRG register for the appropriate baud rate. Set or clear the BRGH bit, as required, to achieve the desired baud rate. 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 3. Ensure bits CREN and SREN are clear. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5. If 9-bit reception is desired, set bit RX9. 6. Verify address detection is disabled by clearing the ADDEN bit of the RCSTA register. 7. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 8. Interrupt flag bit RCIF of the PIR1 register will be set when reception of a character is complete. An interrupt will be generated if the RCIE interrupt enable bit of the PIE1 register was set. 9. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. Read the 8-bit received data by reading the RCREG register. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the AUSART.
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FIGURE 9-8:
RX/DT pin TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit `0' RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. `0'
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TABLE 9-7:
Name INTCON LCDCON LCDSE1 PIE1 PIR1 RCREG RCSTA SSPCON TRISC TXSTA Legend:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 7 GIE Bit 6 PEIE SLPEN SE14 ADIE ADIF RX9 SSPOV TRISC6 TX9 Bit 5 T0IE WERR SE13 RCIE RCIF SREN SSPEN TRISC5 TXEN Bit 4 INTE VLCDEN SE12 TXIE TXIF CREN CKP TRISC4 SYNC Bit 3 RBIE CS1 SE11 SSPIE SSPIF ADDEN SSPM3 TRISC3 -- Bit 2 T0IF CS0 SE10 CCP1IE CCP1IF FERR SSPM2 TRISC2 BRGH Bit 1 INTF LMUX1 SE9 TMR2IE TMR2IF OERR SSPM1 TRISC1 TRMT Bit 0 RBIF LMUX0 SE8 TMR1IE TMR1IF RX9D SSPM0 TRISC0 TX9D Value on POR, BOR 0000 000x 0001 0011 0000 0000 0000 0000 0000 0000 0000 0000 0000 000X 0000 0000 1111 1111 0000 -010 Value on all other Resets 0000 000x 0001 0011 0000 0000 0000 0000 0000 0000 0000 0000 0000 000X 0000 0000 1111 1111 0000 -010
LCDEN SE15 EEIE EEIF SPEN WCOL TRISC7 CSRC
AUSART Receive Data Register
x = unknown, - = unimplemented read as `0'. Shaded cells are not used for Synchronous Master Reception.
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9.3.2 SYNCHRONOUS SLAVE MODE
The following bits are used to configure the AUSART for Synchronous slave operation: * * * * * SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: 1. 2. 3. 4. The first character will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. The TXIF bit will not be set. After the first character has been shifted out of TSR, the TXREG register will transfer the second character to the TSR and the TXIF bit will now be set. If the PEIE and TXIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine.
Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the AUSART. The LCD SEG8 and SEG9 functions must be disabled by clearing the SE8 and SE9 bits of the LCDSE1 register, if the RX/DT and TX/CK pins are shared with the LCD peripheral.
5.
9.3.2.2
1. 2. 3.
Synchronous Slave Transmission Set-up:
9.3.2.1
AUSART Synchronous Slave Transmit
The operation of the Synchronous Master and Slave modes are identical (see Section 9.3.1.2 "Synchronous Master Transmission"), except in the case of the Sleep mode.
4. 5. 6. 7. 8.
Set the SYNC and SPEN bits and clear the CSRC bit. Clear the CREN and SREN bits. If using interrupts, ensure that the GIE and PEIE bits of the INTCON register are set and set the TXIE bit. If 9-bit transmission is desired, set the TX9 bit. Enable transmission by setting the TXEN bit. Verify address detection is disabled by clearing the ADDEN bit of the RCSTA register. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. Start transmission by writing the Least Significant 8 bits to the TXREG register.
TABLE 9-8:
Name INTCON LCDCON LCDSE1 PIE1 PIR1 RCSTA SSPCON TRISC TXREG TXSTA Legend:
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Bit 7 GIE Bit 6 PEIE SLPEN SE14 ADIE ADIF RX9 SSPOV TRISC6 TX9 Bit 5 T0IE WERR SE13 RCIE RCIF SREN SSPEN TRISC5 TXEN Bit 4 INTE VLCDEN SE12 TXIE TXIF CREN CKP TRISC4 SYNC Bit 3 RBIE CS1 SE11 SSPIE SSPIF ADDEN SSPM3 TRISC3 -- Bit 2 T0IF CS0 SE10 CCP1IE CCP1IF FERR SSPM2 TRISC2 BRGH Bit 1 INTF LMUX1 SE9 TMR2IE TMR2IF OERR SSPM1 TRISC1 TRMT Bit 0 RBIF LMUX0 SE8 TMR1IE TMR1IF RX9D SSPM0 TRISC0 TX9D Value on POR, BOR 0000 000x 0001 0011 0000 0000 0000 0000 0000 0000 0000 000X 0000 0000 1111 1111 0000 0000 0000 -010 Value on all other Resets 0000 000x 0001 0011 0000 0000 0000 0000 0000 0000 0000 000X 0000 0000 1111 1111 0000 0000 0000 -010
LCDEN SE15 EEIE EEIF SPEN WCOL TRISC7 CSRC
AUSART Transmit Data Register
x = unknown, - = unimplemented read as `0'. Shaded cells are not used for Synchronous Slave Transmission.
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9.3.2.3 AUSART Synchronous Slave Reception 9.3.2.4
1. 2.
Synchronous Slave Reception Set-up:
The operation of the Synchronous Master and Slave modes is identical (Section 9.3.1.4 "Synchronous Master Reception"), with the following exceptions: * Sleep * CREN bit is always set, therefore the receiver is never Idle * SREN bit, which is a "don't care" in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCREG register. If the RCIE interrupt enable bit of the PIE1 register is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector.
3. 4. 5. 6.
7.
8. 9.
Set the SYNC and SPEN bits and clear the CSRC bit. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit. Verify address detection is disabled by clearing the ADDEN bit of the RCSTA register. Set the CREN bit to enable reception. The RCIF bit of the PIR1 register will be set when reception is complete. An interrupt will be generated if the RCIE bit of the PIE1 register was set. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCSTA register. Retrieve the 8 Least Significant bits from the receive FIFO by reading the RCREG register. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register.
TABLE 9-9:
Name INTCON LCDCON LCDSE1 PIE1 PIR1 RCREG RCSTA SSPCON TRISC TXSTA Legend:
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Bit 7 GIE Bit 6 PEIE SLPEN SE14 ADIE ADIF RX9 SSPOV TRISC6 TX9 Bit 5 T0IE WERR SE13 RCIE RCIF SREN SSPEN TRISC5 TXEN Bit 4 INTE VLCDEN SE12 TXIE TXIF CREN CKP TRISC4 SYNC Bit 3 RBIE CS1 SE11 SSPIE SSPIF ADDEN SSPM3 TRISC3 -- Bit 2 T0IF CS0 SE10 CCP1IE CCP1IF FERR SSPM2 TRISC2 BRGH Bit 1 INTF LMUX1 SE9 TMR2IE TMR2IF OERR SSPM1 TRISC1 TRMT Bit 0 RBIF LMUX0 SE8 TMR1IE TMR1IF RX9D SSPM0 TRISC0 TX9D Value on POR, BOR 0000 000x 0001 0011 0000 0000 0000 0000 0000 0000 0000 0000 0000 000X 0000 0000 1111 1111 0000 -010 Value on all other Resets 0000 000x 0001 0011 0000 0000 0000 0000 0000 0000 0000 0000 0000 000X 0000 0000 1111 1111 0000 -010
LCDEN SE15 EEIE EEIF SPEN WCOL TRISC7 CSRC
AUSART Receive Data Register
x = unknown, - = unimplemented read as `0'. Shaded cells are not used for Synchronous Slave Reception.
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9.4 AUSART Operation During Sleep
9.4.2
The AUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers.
SYNCHRONOUS TRANSMIT DURING SLEEP
To transmit during Sleep, all the following conditions must be met before entering Sleep mode: * RCSTA and TXSTA Control registers must be configured for Synchronous Slave Transmission (see Section 9.3.2.2 "Synchronous Slave Transmission Set-up:"). * The TXIF interrupt flag must be cleared by writing the output data to the TXREG, thereby filling the TSR and transmit buffer. * If interrupts are desired, set the TXIE bit of the PIE1 register and the PEIE bit of the INTCON register. Upon entering Sleep mode, the device will be ready to accept clocks on TX/CK pin and transmit data on the RX/DT pin. When the data word in the TSR has been completely clocked out by the external device, the pending byte in the TXREG will transfer to the TSR and the TXIF flag will be set. Thereby, waking the processor from Sleep. At this point, the TXREG is available to accept another character for transmission, which will clear the TXIF flag. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the GIE global interrupt enable bit is also set then the Interrupt Service Routine at address 0004h will be called.
9.4.1
SYNCHRONOUS RECEIVE DURING SLEEP
To receive during Sleep, all the following conditions must be met before entering Sleep mode: * RCSTA and TXSTA Control registers must be configured for Synchronous Slave Reception (see Section 9.3.2.4 "Synchronous Slave Reception Set-up:"). * If interrupts are desired, set the RCIE bit of the PIE1 register and the PEIE bit of the INTCON register. * The RCIF interrupt flag must be cleared by reading RCREG to unload any pending characters in the receive buffer. Upon entering Sleep mode, the device will be ready to accept data and clocks on the RX/DT and TX/CK pins, respectively. When the data word has been completely clocked in by the external device, the RCIF interrupt flag bit of the PIR1 register will be set. Thereby, waking the processor from Sleep. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the GIE global interrupt enable bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called.
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NOTES:
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10.0 LIQUID CRYSTAL DISPLAY (LCD) DRIVER MODULE
The LCDCON register (Register 10-1) controls the operation of the LCD driver module. The LCDPS register (Register 10-2) configures the LCD clock source prescaler and the type of waveform; Type-A or Type-B. The LCDSE registers (Register 10-3) configure the functions of the port pins. The following LCDSE registers are available: * * * * * * LCDSE0 LCDSE1 LCDSE2 LCDSE3 LCDSE4 LCDSE5 SE<7:0> SE<15:8> SE<23:16>(1) SE<31:24>(2) SE<39:32>(2) SE<41:40>(2)
The Liquid Crystal Display (LCD) driver module generates the timing control to drive a static or multiplexed LCD panel. In the PIC16F913/916 devices, the module drives the panels of up to four commons and up to 16 segments. In the PIC16F914/917 devices, the module drives the panels of up to four commons and up to 24 segments. In the PIC16F946 device, the module drives the panels of up to four commons and up to 42 segments. The LCD module also provides control of the LCD pixel data. The LCD driver module supports: * Direct driving of LCD panel * Three LCD clock sources with selectable prescaler * Up to four commons: - Static (1 common) - 1/2 multiplex (2 commons) - 1/3 multiplex (3 commons) - 1/4 multiplex (4 commons) * Segments up to: - 16 (PIC16F913/916) - 24 (PIC16F914/917) - 42 (PIC16F946) * Static, 1/2 or 1/3 LCD Bias Note: COM3 and SEG15 share the same physical pin on the PIC16F913/916, therefore SEG15 is not available when using 1/4 multiplex displays.
Note 1: PIC16F914/917 and PIC16F946 only. 2: PIC16F946 only. Once the module is initialized for the LCD panel, the individual bits of the LCDDATA<11:0> registers are cleared/set to represent a clear/dark pixel, respectively: * * * * * * * * * * * * LCDDATA0 LCDDATA1 LCDDATA2 LCDDATA3 LCDDATA4 LCDDATA5 LCDDATA6 LCDDATA7 LCDDATA8 LCDDATA9 LCDDATA10 LCDDATA11 SEG<7:0>COM0 SEG<15:8>COM0 SEG<23:16>COM0 SEG<7:0>COM1 SEG<15:8>COM1 SEG<23:16>COM1 SEG<7:0>COM2 SEG<15:8>COM2 SEG<23:16>COM2 SEG<7:0>COM3 SEG<15:8>COM3 SEG<23:16>COM3
10.1
* * * *
LCD Registers
The following additional registers are available on the PIC16F946 only: * * * * * * * * * * * * LCDDATA12 LCDDATA13 LCDDATA14 LCDDATA15 LCDDATA16 LCDDATA17 LCDDATA18 LCDDATA19 LCDDATA20 LCDDATA21 LCDDATA22 LCDDATA23 SEG<31:24>COM0 SEG<39:32>COM0 SEG<41:40>COM0 SEG<31:24>COM1 SEG<39:32>COM1 SEG<41:40>COM1 SEG<31:24>COM2 SEG<39:32>COM2 SEG<41:40>COM2 SEG<31:24>COM3 SEG<39:32>COM3 SEG<41:40>COM3 LCDDATAx is detailed in
The module contains the following registers: LCD Control Register (LCDCON) LCD Phase Register (LCDPS) Up to 6 LCD Segment Enable Registers (LCDSEn) Up to 24 LCD Data Registers (LCDDATA)
TABLE 10-1:
LCD SEGMENT AND DATA REGISTERS
# of LCD Registers Segment Enable 2 3 6 Data 8 12 24
Device PIC16F913/916 PIC16F914/917 PIC16F946
As an example, Register 10-4.
Once the module is configured, the LCDEN bit of the LCDCON register is used to enable or disable the LCD module. The LCD panel can also operate during Sleep by clearing the SLPEN bit of the LCDCON register. Note: The LCDDATA2, LCDDATA5, LCDDATA8 and LCDDATA11 registers are not implemented in the PIC16F913/916 devices.
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FIGURE 10-1: LCD DRIVER MODULE BLOCK DIAGRAM
Data Bus
LCDDATAx Registers
MUX
SEG<41:0>(1, 2, 3) To I/O Pads(1)
Timing Control LCDCON LCDPS LCDSEn COM<3:0>(3)
To I/O Pads(1)
FOSC/8192 T1OSC/32 LFINTOSC/32 Clock Source Select and Prescaler
Note 1: 2: 3:
These are not directly connected to the I/O pads, but may be tri-stated, depending on the configuration of the LCD module. SEG<23:0> on PIC16F914/917, SEG<15:0> on PIC16F913/916. COM3 and SEG15 share the same physical pin on the PIC16F913/916, therefore SEG15 is not available when using 1/4 multiplex displays.
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REGISTER 10-1:
R/W-0 LCDEN bit 7 Legend: R = Readable bit C = Only clearable bit -n = Value at POR bit 7 LCDEN: LCD Driver Enable bit 1 = LCD driver module is enabled 0 = LCD driver module is disabled SLPEN: LCD Driver Enable in Sleep mode bit 1 = LCD driver module is disabled in Sleep mode 0 = LCD driver module is enabled in Sleep mode WERR: LCD Write Failed Error bit 1 = LCDDATAx register written while the WA bit of the LCDPS register = 0 (must be cleared in software) 0 = No LCD write error VLCDEN: LCD Bias Voltage Pins Enable bit 1 = VLCD pins are enabled 0 = VLCD pins are disabled CS<1:0>: Clock Source Select bits 00 = FOSC/8192 01 = T1OSC (Timer1)/32 1x = LFINTOSC (31 kHz)/32 LMUX<1:0>: Commons Select bits LMUX<1:0> 00 01 10 11 Multiplex Static (COM0) 1/2 (COM<1:0>) 1/3 (COM<2:0>) 1/4 (COM<3:0>) Maximum Number of Pixels PIC16F913/916 16 32 48 60(1) PIC16F914/917 24 48 72 96 PIC16F946 42 84 126 168 Bias Static 1/2 or 1/3 1/2 or 1/3 1/3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
LCDCON: LIQUID CRYSTAL DISPLAY CONTROL REGISTER
R/W-0 R/C-0 WERR R/W-1 VLCDEN R/W-0 CS1 R/W-0 CS0 R/W-1 LMUX1 R/W-1 LMUX0 bit 0
SLPEN
bit 6
bit 5
bit 4
bit 3-2
bit 1-0
Note 1:
On PIC16F913/916 devices, COM3 and SEG15 are shared on one pin, limiting the device from driving 64 pixels.
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REGISTER 10-2:
R/W-0 WFT bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
LCDPS: LCD PRESCALER SELECT REGISTER
R/W-0 R-0 LCDA R-0 WA R/W-0 LP3 R/W-0 LP2 R/W-0 LP1 R/W-0 LP0 bit 0
BIASMD
WFT: Waveform Type Select bit 1 = Type-B waveform (phase changes on each frame boundary) 0 = Type-A waveform (phase changes within each common interval) BIASMD: Bias Mode Select bit When LMUX<1:0> = 00: 0 = Static Bias mode (do not set this bit to `1') When LMUX<1:0> = 01: 1 = 1/2 Bias mode 0 = 1/3 Bias mode When LMUX<1:0> = 10: 1 = 1/2 Bias mode 0 = 1/3 Bias mode When LMUX<1:0> = 11: 0 = 1/3 Bias mode (do not set this bit to `1') LCDA: LCD Active Status bit 1 = LCD driver module is active 0 = LCD driver module is inactive WA: LCD Write Allow Status bit 1 = Write into the LCDDATAx registers is allowed 0 = Write into the LCDDATAx registers is not allowed LP<3:0>: LCD Prescaler Select bits 1111 = 1:16 1110 = 1:15 1101 = 1:14 1100 = 1:13 1011 = 1:12 1010 = 1:11 1001 = 1:10 1000 = 1:9 0111 = 1:8 0110 = 1:7 0101 = 1:6 0100 = 1:5 0011 = 1:4 0010 = 1:3 0001 = 1:2 0000 = 1:1
bit 6
bit 5
bit 4
bit 3-0
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REGISTER 10-3:
R/W-0 SEn bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
LCDSEn: LCD SEGMENT ENABLE REGISTERS
R/W-0 SEn R/W-0 SEn R/W-0 SEn R/W-0 SEn R/W-0 SEn R/W-0 SEn R/W-0 SEn bit 0
SEn: Segment Enable bits 1 = Segment function of the pin is enabled 0 = I/O function of the pin is enabled
REGISTER 10-4:
R/W-x bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
LCDDATAx: LCD DATA REGISTERS
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x bit 0
R/W-x
SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
SEGx-COMy: Pixel On bits 1 = Pixel on (dark) 0 = Pixel off (clear)
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10.2 LCD Clock Source Selection
10.2.1 LCD PRESCALER
The LCD driver module has 3 possible clock sources: * FOSC/8192 * T1OSC/32 * LFINTOSC/32 The first clock source is the system clock divided by 8192 (FOSC/8192). This divider ratio is chosen to provide about 1 kHz output when the system clock is 8 MHz. The divider is not programmable. Instead, the LCD prescaler bits LP<3:0> of the LCDPS register are used to set the LCD frame clock rate. The second clock source is the T1OSC/32. This also gives about 1 kHz when a 32.768 kHz crystal is used with the Timer1 oscillator. To use the Timer1 oscillator as a clock source, the T1OSCEN bit of the T1CON register should be set. The third clock source is the 31 kHz LFINTOSC/32, which provides approximately 1 kHz output. The second and third clock sources may be used to continue running the LCD while the processor is in Sleep. Using bits CS<1:0> of the LCDCON register can select any of these clock sources. A 4-bit counter is available as a prescaler for the LCD clock. The prescaler is not directly readable or writable; its value is set by the LP<3:0> bits of the LCDPS register, which determine the prescaler assignment and prescale ratio. The prescale values are selectable from 1:1 through 1:16.
10.3
LCD Bias Types
The LCD driver module can be configured into one of three bias types: * Static Bias (2 voltage levels: VSS and VDD) * 1/2 Bias (3 voltage levels: VSS, 1/2 VDD and VDD) * 1/3 Bias (4 voltage levels: VSS, 1/3 VDD, 2/3 VDD and VDD) This module uses an external resistor ladder to generate the LCD bias voltages. The external resistor ladder should be connected to the VLCD1 pin (Bias 1), VLCD2 pin (Bias 2), VLCD3 pin (Bias 3) and VSS. The VLCD3 pin should also be connected to VDD. Figure 10-2 shows the proper way to connect the resistor ladder to the Bias pins.. Note: VLCD pins used to supply LCD bias voltage are enabled on power-up (POR) and must be disabled by the user by clearing the VLCDEN bit of the LCDCON register.
FIGURE 10-2:
LCD BIAS RESISTOR LADDER CONNECTION DIAGRAM
Static Bias VLCD 0 VLCD 3 To VLCD 2 LCD VLCD 1 (1) Driver VLCD 0 VLCD 1 VLCD 2 VLCD 3 VSS -- -- VDD 1/2 Bias VSS 1/2 VDD 1/2 VDD VDD 1/3 Bias VSS 1/3 VDD 2/3 VDD VDD
LCD Bias 3 VDD* VDD* 10 k*
LCD Bias 2
LCD Bias 1
Connections for External R-ladder Static Bias 1/2 Bias VSS
10 k*
VDD*
10 k*
10 k*
10 k* VSS
1/3 Bias
* Note 1:
These values are provided for design guidance only and should be optimized for the application by the designer. Internal connection.
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10.4 LCD Multiplex Types 10.7 LCD Frame Frequency
The LCD driver module can be configured into one of four multiplex types: * * * * Static (only COM0 is used) 1/2 multiplex (COM<1:0> are used) 1/3 multiplex (COM<2:0> are used) 1/4 multiplex (COM<3:0> are used) The rate at which the COM and SEG outputs change is called the LCD frame frequency.
TABLE 10-3:
Multiplex Static 1/2 1/3 1/4 Note:
FRAME FREQUENCY FORMULAS
Frame Frequency = Clock source/(4 x 1 x (LP<3:0> + 1)) Clock source/(2 x 2 x (LP<3:0> + 1)) Clock source/(1 x 3 x (LP<3:0> + 1)) Clock source/(1 x 4 x (LP<3:0> + 1))
The LMUX<1:0> bit setting of the LCDCON register decides the function of RB5, RA2 or either RA3 or RD0 pins (see Table 10-2 for details). If the pin is a digital I/O, the corresponding TRIS bit controls the data direction. If the pin is a COM drive, then the TRIS setting of that pin is overridden. Note: On a Power-on Reset, the LMUX<1:0> bits of the LCDCON register are `11'.
Clock source is FOSC/8192, T1OSC/32 or LFINTOSC/32.
TABLE 10-4:
TABLE 10-2:
Multiplex Static 1/2 1/3 1/4 Note 1: LMUX <1:0> 00 01 10 11
RA3/RD0, RA2, RB5 FUNCTION
RA3/RD0(1) Digital I/O Digital I/O Digital I/O RA2 Digital I/O Digital I/O RB5 Digital I/O COM1 Driver
APPROXIMATE FRAME FREQUENCY (IN Hz) USING FOSC @ 8 MHz, TIMER1 @ 32.768 kHz OR LFINTOSC
Static 85 64 51 43 37 32 1/2 85 64 51 43 37 32 1/3 114 85 68 57 49 43 1/4 85 64 51 43 37 32
LP<3:0> 2 3 4 5 6 7
COM2 Driver COM1 Driver
COM3 Driver COM2 Driver COM1 Driver
RA3 for PIC16F913/916, RD0 for PIC16F914/917 and PIC16F946
10.5
Segment Enables
The LCDSEn registers are used to select the pin function for each segment pin. The selection allows each pin to operate as either an LCD segment driver or as one of the pin's alternate functions. To configure the pin as a segment pin, the corresponding bits in the LCDSEn registers must be set to `1'. If the pin is a digital I/O, the corresponding TRIS bit controls the data direction. Any bit set in the LCDSEn registers overrides any bit settings in the corresponding TRIS register. Note: On a Power-on Reset, these pins are configured as digital I/O.
10.6
Pixel Control
The LCDDATAx registers contain bits which define the state of each pixel. Each bit defines one unique pixel. Register 10-4 shows the correlation of each bit in the LCDDATAx registers to the respective common and segment signals. Any LCD pixel location not being used for display can be used as general purpose RAM.
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FIGURE 10-3:
FOSC
LCD CLOCK GENERATION
/8192 COM0 COM1 COM2 COM3 /4 /32 /2 1/2 1/3, 1/4 LP<3:0> (LCDPS<3:0>) LMUX<1:0> (LCDCON<1:0>) LMUX<1:0> (LCDCON<1:0>) 4-bit Prog Presc Static /1, 2, 3, 4 Ring Counter /32 CS<1:0> (LCDCON<3:2>)
(c) 2007 Microchip Technology Inc.
T1OSC 32 kHz Crystal Osc.
LFINTOSC Nominal = 31 kHz
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FIGURE 10-4:
LCD Function LCDDATAx Address 28-pin 21 22 23 24 6 7 14 3 18 17 16 15 2 28 27 5 -- LCDDATA11, 1 LCDDATA11, 2 LCDDATA11, 3 LCDDATA11, 4 LCDDATA11, 5 LCDDATA11, 6 LCDDATA8, 7 LCDDATA11, 7 -- -- -- -- -- -- -- 3 26 25 24 23 2 40 39 5 26 27 28 29 30 8 9 10 18 7 6 31 32 52 28 62 61 60 59 27 24 23 30 58 63 64 1 2 33 34 35 36 18 35 17 RB2 RB3 RA4 RA5 RC3 RA1 RC7 RC6 RC5 RC4 RA0 RB7 RB6 RA3 RD3 RD4 RD5 RD6 RD7 RE0 RE1 RE2 34 16 RB1 33 15 RB0 40-pin 64-pin LCDDATA3, 0 LCDDATA3, 1 LCDDATA3, 2 LCDDATA3, 3 LCDDATA3, 4 LCDDATA3, 5 LCDDATA3, 6 LCDDATA3, 7 LCDDATA4, 0 LCDDATA4, 1 LCDDATA4, 2 LCDDATA4, 3 LCDDATA4, 4 LCDDATA4, 5 LCDDATA4, 6 LCDDATA4, 7 LCDDATA5, 0 LCDDATA5, 1 LCDDATA5, 2 LCDDATA5, 3 LCDDATA5, 4 LCDDATA5, 5 LCDDATA5, 6 LCDDATA5, 7 LCDDATA8, 4 LCDDATA8, 5 LCDDATA8, 6 LCDDATA8, 3 LCDDATA8, 2 LCDDATA8, 1 LCDDATA8, 0 LCDDATA7, 7 LCDDATA7, 6 LCDDATA7, 5 LCDDATA10, 5 LCDDATA10, 6 LCDDATA10, 7 LCDDATA11, 0 LCDDATA7, 4 LCDDATA10, 4 LCDDATA7, 3 LCDDATA10, 3 LCDDATA7, 2 LCDDATA10, 2 LCDDATA7, 1 LCDDATA10, 1 LCDDATA7, 0 LCDDATA10, 0 LCDDATA6, 7 LCDDATA9, 7 LCDDATA6, 6 LCDDATA9, 6 LCDDATA6, 5 LCDDATA9, 5 LCDDATA6, 4 LCDDATA9, 4 LCDDATA6, 3 LCDDATA9, 3 LCDDATA6, 2 LCDDATA9, 2 LCDDATA6, 1 LCDDATA9, 1 LCDDATA6, 0 LCDDATA9, 0 LCD Segment LCDDATAx Address LCD Segment LCDDATAx Address LCD Segment PORT
COM0
COM1
COM2
COM3
Pin No.
LCDDATAx Address
LCD Segment
Alternate Functions INT
SEG0
LCDDATA0, 0
SEG1
LCDDATA0, 1
(c) 2007 Microchip Technology Inc.
C1OUT/T0CKI C2OUT/AN4/SS AN1/C2RX/DT/SDI/SDA TX/CK/SCK/SCL T1CKI/CCP1 T1G/SDO AN0/C1ICSPDAT/ICDDAT ICSPCLK/ICDCK AN3/VREF+/COM3* AN5 AN6 AN7
SEG2
LCDDATA0, 2
SEG3
LCDDATA0, 3
SEG4
LCDDATA0, 4
SEG5
LCDDATA0, 5
SEG6
LCDDATA0, 6
SEG7
LCDDATA0, 7
SEG8
LCDDATA1, 0
SEG9
LCDDATA1, 1
SEG10
LCDDATA1, 2
SEG11
LCDDATA1, 3
SEG12
LCDDATA1, 4
SEG13
LCDDATA1, 5
SEG14
LCDDATA1, 6
SEG15
LCDDATA1, 7
SEG16
LCDDATA2, 0
SEG17
LCDDATA2, 1
LCD SEGMENT MAPPING WORKSHEET (SHEET 1 OF 2)
SEG18
LCDDATA2, 2
SEG19
LCDDATA2, 3
SEG20
LCDDATA2, 4
SEG21
LCDDATA2, 5
SEG22
LCDDATA2, 6
SEG23
LCDDATA2, 7
PIC16F913/914/916/917/946
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PIC16F914/917 and PIC16F946 only. * = PIC16F913/916 only.
FIGURE 10-5:
DS41250F-page 152
COM1 LCD Segment LCDDATA15, 0 LCDDATA15, 1 LCDDATA15, 2 LCDDATA15, 3 LCDDATA15, 4 LCDDATA15, 5 LCDDATA15, 6 LCDDATA15, 7 LCDDATA16, 0 LCDDATA16, 1 LCDDATA16, 2 LCDDATA16, 3 LCDDATA16, 4 LCDDATA16, 5 LCDDATA16, 6 LCDDATA16, 7 LCDDATA17, 0 LCDDATA17, 1 LCDDATA20, 1 LCDDATA20, 0 LCDDATA19, 7 LCDDATA19, 6 LCDDATA19, 5 LCDDATA19, 4 LCDDATA22, 4 LCDDATA22, 5 LCDDATA22, 6 LCDDATA22, 7 LCDDATA23, 0 LCDDATA23, 1 LCDDATA19, 3 LCDDATA22, 3 LCDDATA19, 2 LCDDATA22, 2 LCDDATA19, 1 LCDDATA22, 1 LCDDATA19, 0 LCDDATA22, 0 LCDDATA18, 7 LCDDATA21, 7 LCDDATA18, 6 LCDDATA21, 6 47 48 11 12 13 14 3 4 5 6 7 8 LCDDATA18, 5 LCDDATA21, 5 46 LCDDATA18, 4 LCDDATA21, 4 45 LCDDATA18, 3 LCDDATA21, 3 44 RE7 RF4 RF5 RF6 RF7 RF0 RF1 RF2 RF3 RG0 RG1 RG2 RG3 RG4 RG5 LCDDATA18, 2 LCDDATA21, 2 43 RE6 LCDDATA18, 1 LCDDATA21, 1 42 RE5 LCDDATA18, 0 LCDDATA21, 0 37 RE4 LCDDATAx Address LCD Segment LCDDATAx Address LCD Segment LCDDATAx Address LCD Segment 64-pin COM2 COM3 Pin No. PORT Alternate Functions
LCD Function
COM0
LCDDATAx Address
SEG24
LCDDATA12, 0
SEG25
LCDDATA12, 1
SEG26
LCDDATA12, 2
SEG27
LCDDATA12, 3
SEG28
LCDDATA12, 4
SEG29
LCDDATA12, 5
SEG30
LCDDATA12, 6
SEG31
LCDDATA12, 7
SEG32
LCDDATA13, 0
SEG33
LCDDATA13, 1
SEG34
LCDDATA13, 2
SEG35
LCDDATA13, 3
SEG36
LCDDATA13, 4
PIC16F913/914/916/917/946
SEG37
LCDDATA13, 5
SEG38
LCDDATA13, 6
SEG39
LCDDATA13, 7
SEG40
LCDDATA14, 0
SEG41
LCDDATA14, 1
LCD SEGMENT MAPPING WORKSHEET (SHEET 2 OF 2)
(c) 2007 Microchip Technology Inc.
PIC16F946 only.
PIC16F913/914/916/917/946
10.8 LCD Waveform Generation
LCD waveforms are generated so that the net AC voltage across the dark pixel should be maximized and the net AC voltage across the clear pixel should be minimized. The net DC voltage across any pixel should be zero. The COM signal represents the time slice for each common, while the SEG contains the pixel data. The pixel signal (COM-SEG) will have no DC component and it can take only one of the two rms values. The higher rms value will create a dark pixel and a lower rms value will create a clear pixel. As the number of commons increases, the delta between the two rms values decreases. The delta represents the maximum contrast that the display can have. The LCDs can be driven by two types of waveform: Type-A and Type-B. In Type-A waveform, the phase changes within each common type, whereas in Type-B waveform, the phase changes on each frame boundary. Thus, Type-A waveform maintains 0 VDC over a single frame, whereas Type-B waveform takes two frames. Note 1: If Sleep has to be executed with LCD Sleep disabled (LCDCON is `1'), then care must be taken to execute Sleep only when VDC on all the pixels is `0'. 2: When the LCD clock source is FOSC/8192, if Sleep is executed, irrespective of the LCDCON setting, the LCD goes into Sleep. Thus, take care to see that VDC on all pixels is `0' when Sleep is executed. Figure 10-6 through Figure 10-16 provide waveforms for static, half-multiplex, one-third-multiplex and quarter-multiplex drives for Type-A and Type-B waveforms.
FIGURE 10-6:
TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE
COM0 COM0 SEG0
V1 V0 V1 V0 V1 V0 V1
SEG1
COM0-SEG0
V0 -V1
COM0-SEG1 1 Frame SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0
V0
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FIGURE 10-7: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE
V2 COM0 COM1 COM1 V1 V0 V2 COM0 V1 V0 V2 SEG0 V1 V0 V2 SEG1 V1 V0 V2 V1 V0 -V1 -V2 V2 V1 COM0-SEG1 V0 -V1 1 Frame -V2
SEG3
SEG2
SEG1 SEG0 COM0-SEG0
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FIGURE 10-8: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE
V2 COM1 COM0 V1 V0
COM0 COM1
V2 V1 V0
SEG0
V2 V1 V0
SEG2
SEG1 SEG0
SEG3
SEG1
V2 V1 V0
V2 V1 COM0-SEG0 V0 -V1 -V2
V2 V1 COM0-SEG1 V0 -V1 2 Frames -V2
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FIGURE 10-9: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE
V3 COM0 COM1 V2 V1 V0 V3 COM1 V2 V1 V0 V3 SEG0 V2 V1 V0 V3 SEG3 SEG2 SEG1 SEG0 SEG1 V2 V1 V0
COM0
V3 V2 V1 COM0-SEG0 V0 -V1 -V2 -V3
V3 V2 V1 COM0-SEG1 V0 -V1 1 Frame -V2 -V3
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FIGURE 10-10: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE
V3 COM0 COM1 V2 V1 V0 COM0 COM1 V3 V2 V1 V0 V3 SEG0 V2 V1 V0 V3 SEG3 SEG2 SEG1 SEG0 SEG1 V2 V1 V0
V3 V2 V1 COM0-SEG0 V0 -V1 -V2 -V3
V3 V2 V1 COM0-SEG1 V0 -V1 2 Frames -V2 -V3
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FIGURE 10-11: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE
V2 V1 V0 V2 COM2 COM1 V1 V0 COM1 COM0 COM2 V2 V1 V0 SEG0 SEG2 V2 V1 V0 V2 SEG1 SEG2 SEG1 SEG0 V1 V0 V2 V1 COM0-SEG0 V0 -V1 -V2 V2 V1 COM0-SEG1 V0 -V1 -V2 1 Frame
COM0
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PIC16F913/914/916/917/946
FIGURE 10-12: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE
COM0
V2 V1 V0
COM2 COM1 COM1 COM0 V2 V1 V0 V2 V1 V0 V2 V1 V0 V2 V1 V0 V2 V1 COM0-SEG0 V0 -V1 -V2
COM2
SEG0 SEG2 SEG1 SEG0
SEG1
V2 V1 COM0-SEG1 V0 -V1 -V2 2 Frames
(c) 2007 Microchip Technology Inc.
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FIGURE 10-13: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE
V3 COM0 V2 V1 V0 COM2 COM1 COM1 COM0 V3 V2 V1 V0 V3 COM2 V2 V1 V0 V3 SEG0 SEG2 SEG2 SEG1 SEG0 V2 V1 V0 V3 SEG1 V2 V1 V0 V3 V2 V1 COM0-SEG0 V0 -V1 -V2 -V3 V3 V2 V1 COM0-SEG1 V0 -V1 -V2 -V3 1 Frame
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FIGURE 10-14: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE
V3 COM0 V2 V1 V0 COM2 COM1 COM1 COM0 V3 V2 V1 V0 V3 COM2 V2 V1 V0 V3 SEG0 SEG2 SEG1 SEG0 V2 V1 V0 V3 SEG1 V2 V1 V0 V3 V2 V1 COM0-SEG0 V0 -V1 -V2 -V3 V3 V2 V1 COM0-SEG1 V0 -V1 -V2 -V3 2 Frames
(c) 2007 Microchip Technology Inc.
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FIGURE 10-15:
COM3 COM2 COM0
TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE
V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 -V1 -V2 -V3 V3 V2 V1 V0 -V1 -V2 -V3
COM1 COM0
COM1
COM2
COM3
SEG0 SEG1 SEG0
SEG1
COM0-SEG0
COM0-SEG1 1 Frame
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FIGURE 10-16:
COM3 COM2 COM0
TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE
V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 -V1 -V2 -V3 V3 V2 V1 V0 -V1 -V2 -V3
COM1 COM0
COM1
COM2
COM3
SEG0 SEG1 SEG0
SEG1
COM0-SEG0
COM0-SEG1 2 Frames
(c) 2007 Microchip Technology Inc.
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10.9 LCD Interrupts
The LCD timing generation provides an interrupt that defines the LCD frame timing. A new frame is defined to begin at the leading edge of the COM0 common signal. The interrupt will be set immediately after the LCD controller completes accessing all pixel data required for a frame. This will occur at a fixed interval before the frame boundary (TFINT), as shown in Figure 10-17. The LCD controller will begin to access data for the next frame within the interval from the interrupt to when the controller begins to access data after the interrupt (TFWR). New data must be written within TFWR, as this is when the LCD controller will begin to access the data for the next frame. When the LCD driver is running with Type-B waveforms and the LMUX<1:0> bits are not equal to `00' (static drive), there are some additional issues that must be addressed. Since the DC voltage on the pixel takes two frames to maintain zero volts, the pixel data must not change between subsequent frames. If the pixel data were allowed to change, the waveform for the odd frames would not necessarily be the complement of the waveform generated in the even frames and a DC component would be introduced into the panel. Therefore, when using Type-B waveforms, the user must synchronize the LCD pixel updates to occur within a subframe after the frame interrupt. To correctly sequence writing while in Type-B, the interrupt will only occur on complete phase intervals. If the user attempts to write when the write is disabled, the WERR bit of the LCDCON register is set and the write does not occur. Note: The interrupt is not generated when the Type-A waveform is selected and when the Type-B with no multiplex (static) is selected.
FIGURE 10-17:
WAVEFORMS AND INTERRUPT TIMING IN QUARTER-DUTY CYCLE DRIVE (EXAMPLE - TYPE-B, NON-STATIC)
LCD Interrupt Occurs Controller Accesses Next Frame Data V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0
COM0
COM1
COM2
COM3
2 Frames TFINT Frame Boundary TFWR = TFRAME/2*(LMUX<1:0> + 1) + TCY/2 TFINT = (TFWR/2 - (2 TCY + 40 ns)) minimum = 1.5(TFRAME/4) - (2 TCY + 40 ns) (TFWR/2 - (1 TCY + 40 ns)) maximum = 1.5(TFRAME/4) - (1 TCY + 40 ns) Frame Boundary TFWR Frame Boundary
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10.10 Operation During Sleep
The LCD module can operate during Sleep. The selection is controlled by bit SLPEN of the LCDCON register. Setting the SLPEN bit allows the LCD module to go to Sleep. Clearing the SLPEN bit allows the module to continue to operate during Sleep. If a SLEEP instruction is executed and SLPEN = 1, the LCD module will cease all functions and go into a very low-current Consumption mode. The module will stop operation immediately and drive the minimum LCD voltage on both segment and common lines. Figure 10-18 shows this operation. To ensure that no DC component is introduced on the panel, the SLEEP instruction should be executed immediately after a LCD frame boundary. For Type-B multiplex (non-static), the LCD interrupt can be used to determine the frame boundary. See Section 10.9 "LCD Interrupts" for the formulas to calculate the delay. In all other modes, the LCDA bit can be used to determine when the display is active. To use this method, the following sequence should be used when wanting to enter into Sleep mode: * Clear LCDEN * Wait for LCDA to clear * Drive all LCD pins to inactive state using PORT and TRIS registers * Execute SLEEP instruction Note: When the LCDEN bit is cleared, the LCD module will be disabled at the completion of frame. At this time, the PORT pins will revert to digital functionality. To minimize power consumption due to floating digital inputs, the LCD pins should be driven low using the PORT and TRIS registers. Table 10-5 shows the status of the LCD module during a Sleep while using each of the three available clock sources:
TABLE 10-5:
Clock Source T1OSC LFINTOSC FOSC/4
LCD MODULE STATUS DURING SLEEP
SLPEN 0 1 0 1 0 1 Operation During Sleep? Yes No Yes No No No
Note:
The LFINTOSC or external T1OSC oscillator must be used to operate the LCD module during Sleep.
If LCD interrupts are being generated (Type-B waveform with a multiplex mode not static) and LCDIE = 1, the device will awaken from Sleep on the next frame boundary.
If a SLEEP instruction is executed and SLPEN = 0, the module will continue to display the current contents of the LCDDATA registers. To allow the module to continue operation while in Sleep, the clock source must be either the LFINTOSC or T1OSC external oscillator. While in Sleep, the LCD data cannot be changed. The LCD module current consumption will not decrease in this mode; however, the overall consumption of the device will be lower due to shut down of the core and other peripheral functions.
(c) 2007 Microchip Technology Inc.
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FIGURE 10-18: SLEEP ENTRY/EXIT WHEN SLPEN = 1
V3 V2 V1 COM0 V0 V3 V2 V1 COM1 V0 V3 V2 V1 COM2 V0 V3 V2 V1 SEG0 2 Frames SLEEP Instruction Execution Wake-up V0
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10.11 Configuring the LCD Module
The following is the sequence of steps to configure the LCD module. 1. 2. 3. Select the frame clock prescale using bits LP<3:0> of the LCDPS register. Configure the appropriate pins to function as segment drivers using the LCDSEn registers. Configure the LCD module for the following using the LCDCON register: - Multiplex and Bias mode, bits LMUX<1:0> - Timing source, bits CS<1:0> - Sleep mode, bit SLPEN Write initial values to pixel data registers, LCDDATA0 through LCDDATA11 (LCDDATA23 on PIC16F946). Clear LCD Interrupt Flag, LCDIF bit of the PIR2 register and if desired, enable the interrupt by setting bit LCDIE of the PIE2 register. Enable bias voltage pins (VLCD<3:1>) by setting bit VLCDEN of the LCDCON register. Enable the LCD module by setting bit LCDEN of the LCDCON register.
10.13 LCD Current Consumption
When using the LCD module the current consumption consists of the following three factors: 1. 2. 3. The oscillator selected The LCD bias source The current required to charge the LCD segments
The current consumption of just the LCD module can be considered negligible compared to these other factors. The oscillator selected: For LCD operation during Sleep either the T1oc or the LFINTOSC sources need to be used as the main system oscillator may be disabled during Sleep. During Sleep the LFINTOSC current consumption is given by electrical parameter D021, where the LFINTOSC use the same internal oscillator circuitry as the Watchdog Timer. The LCD bias source: The LCD bias source, typically an external resistor ladder which will have its own current draw. The current required to charge the LCD segments: The LCD segments which can be modeled as capacitors which must be both charged and discharged every frame. The size of the LCD segment and its technology determines the segment's capacitance.
4.
5.
6. 7.
10.12 Disabling the LCD Module
To disable the LCD module, write all `0's to the LCDCON register.
(c) 2007 Microchip Technology Inc.
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TABLE 10-6:
Name CMCON0 INTCON LCDCON LCDDATA0 LCDDATA1 LCDDATA2(2) LCDDATA3 LCDDATA4 LCDDATA5(2) LCDDATA6 LCDDATA7 LCDDATA8(2) LCDDATA9 LCDDATA10 LCDDATA11(2) LCDDATA12(3) LCDDATA13(3) LCDDATA14(3) LCDDATA15(3) LCDDATA16(3) LCDDATA17(3) LCDDATA18(3) LCDDATA19(3) LCDDATA20(3) LCDDATA21(3) LCDDATA22(3) LCDDATA23(3) LCDPS LCDSE0 LCDSE1 Legend: Note 1: 2: 3:
REGISTERS ASSOCIATED WITH LCD OPERATION
Bit 7 C2OUT GIE LCDEN SEG7 COM0 SEG15 COM0 SEG23 COM0 SEG7 COM1 SEG15 COM1 SEG23 COM1 SEG7 COM2 SEG15 COM2 SEG23 COM2 SEG7 COM3 SEG15 COM3 SEG23 COM3 SEG31 COM0 SEG39 COM0 -- SEG31 COM1 SEG39 COM1 -- SEG31 COM2 SEG39 COM2 -- SEG31 COM3 SEG39 COM3 -- WFT SE7 SE15 Bit 6 C1OUT PEIE SLPEN SEG6 COM0 SEG14 COM0 SEG22 COM0 SEG6 COM1 SEG14 COM1 SEG22 COM1 SEG6 COM2 SEG14 COM2 SEG22 COM2 SEG6 COM3 SEG14 COM3 SEG22 COM3 SEG30 COM0 SEG38 COM0 -- SEG30 COM1 SEG38 COM1 -- SEG30 COM2 SEG38 COM2 -- SEG30 COM3 SEG38 COM3 -- BIASMD SE6 SE14 Bit 5 C2INV T0IE WERR SEG5 COM0 SEG13 COM0 SEG21 COM0 SEG5 COM1 SEG13 COM1 SEG21 COM1 SEG5 COM2 SEG13 COM2 SEG21 COM2 SEG5 COM3 SEG13 COM3 SEG21 COM3 SEG29 COM0 SEG37 COM0 -- SEG29 COM1 SEG37 COM1 -- SEG29 COM2 SEG37 COM2 -- SEG29 COM3 SEG37 COM3 -- LCDA SE5 SE13 Bit 4 C1INV INTE VLCDEN SEG4 COM0 SEG12 COM0 SEG20 COM0 SEG4 COM1 SEG12 COM1 SEG20 COM1 SEG4 COM2 SEG12 COM2 SEG20 COM2 SEG4 COM3 SEG12 COM3 SEG20 COM3 SEG28 COM0 SEG36 COM0 -- SEG28 COM1 SEG36 COM1 -- SEG28 COM2 SEG36 COM2 -- SEG28 COM3 SEG36 COM3 -- WA SE4 SE12 Bit 3 CIS RBIE CS1 SEG3 COM0 SEG11 COM0 SEG19 COM0 SEG3 COM1 SEG11 COM1 SEG19 COM1 SEG3 COM2 SEG11 COM2 SEG19 COM2 SEG3 COM3 SEG11 COM3 SEG19 COM3 SEG27 COM0 SEG35 COM0 -- SEG27 COM1 SEG35 COM1 -- SEG27 COM2 SEG35 COM2 -- SEG27 COM3 SEG35 COM3 -- LP3 SE3 SE11 Bit 2 CM2 T0IF CS0 SEG2 COM0 SEG10 COM0 SEG18 COM0 SEG2 COM1 SEG10 COM1 SEG18 COM1 SEG2 COM2 SEG10 COM2 SEG18 COM2 SEG2 COM3 SEG10 COM3 SEG18 COM3 SEG26 COM0 SEG34 COM0 -- SEG26 COM1 SEG34 COM1 -- SEG26 COM2 SEG34 COM2 -- SEG26 COM3 SEG34 COM3 -- LP2 SE2 SE10 Bit 1 CM1 INTF LMUX1 SEG1 COM0 SEG9 COM0 SEG17 COM0 SEG1 COM1 SEG9 COM1 SEG17 COM1 SEG1 COM2 SEG9 COM2 SEG17 COM2 SEG1 COM3 SEG9 COM3 SEG17 COM3 SEG25 COM0 SE33 COM0 SEG41 COM0 SEG25 COM1 SEG33 COM1 SEG41 COM1 SEG25 COM2 SEG33 COM2 SEG41 COM2 SEG25 COM3 SEG33 COM3 SEG41 COM3 LP1 SE1 SE9 Bit 0 CM0 RBIF LMUX0 SEG0 COM0 SEG8 COM0 SEG16 COM0 SEG0 COM1 SEG8 COM1 SEG16 COM1 SEG0 COM2 SEG8 COM2 SEG16 COM2 SEG0 COM3 SEG8 COM3 SEG16 COM3 SEG24 COM0 SEG32 COM0 SEG40 COM0 SEG24 COM1 SEG32 COM1 SEG40 COM1 SEG24 COM2 SEG32 COM2 SEG40 COM2 SEG24 COM3 SEG32 COM3 SEG40 COM3 LP0 SE0 SE8 Value on POR, BOR 0000 0000 0000 000x 0001 0011 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ---- --xx xxxx xxxx xxxx xxxx ---- --xx xxxx xxxx xxxx xxxx ---- --xx xxxx xxxx xxxx xxxx ---- --xx 0000 0000 0000 0000 0000 0000 Value on all other Resets 0000 0000 0000 000x 0001 0011 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu uuuu uuuu ---- --uu 0000 0000 uuuu uuuu uuuu uuuu
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the LCD module. These pins may be configured as port pins, depending on the oscillator mode selected. PIC16F914/917 and PIC16F946 only. PIC16F946 only.
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TABLE 10-6:
Name LCDSE2(2) LCDSE3(3) LCDSE4(3) LCDSE5(3) PIE2 PIR2 T1CON Legend: Note 1: 2: 3:
REGISTERS ASSOCIATED WITH LCD OPERATION (CONTINUED)
Bit 7 SE23 SE31 SE39 -- OSFIE OSFIF T1GINV Bit 6 SE22 SE30 SE38 -- C2IE C2IF TMR1GE Bit 5 SE21 SE29 SE37 -- C1IE C1IF T1CKPS1 Bit 4 SE20 SE28 SE36 -- LCDIE LCDIF T1CKPS0 Bit 3 SE19 SE27 SE35 -- -- -- T1OSCEN Bit 2 SE18 SE26 SE34 -- LVDIE LVDIF T1SYNC Bit 1 SE17 SE25 SE33 SE41 -- -- TMR1CS Bit 0 SE16 SE24 SE32 SE40 CCP2IE CCP2IF TMR1ON Value on POR, BOR 0000 0000 0000 0000 0000 0000 ---- --00 0000 -0-0 0000 -0-0 0000 0000 Value on all other Resets uuuu uuuu 0000 0000 0000 0000 ---- --00 0000 -0-0 0000 -0-0 uuuu uuuu
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the LCD module. These pins may be configured as port pins, depending on the oscillator mode selected. PIC16F914/917 and PIC16F946 only. PIC16F946 only.
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NOTES:
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11.0 PROGRAMMABLE LOW-VOLTAGE DETECT (PLVD) MODULE
The PLVD module includes the following capabilities: * * * * Eight programmable trip points Interrupt on falling VDD Stable reference indication Operation during Sleep
The Programmable Low-Voltage Detect (PLVD) module is a power supply detector which monitors the internal power supply. This module is typically used in key fobs and other devices, where certain actions need to be taken as a result of a falling battery voltage.
A Block diagram of the PLVD module is shown in Figure 11-1.
FIGURE 11-1:
PLVD BLOCK DIAGRAM
8 Stages
VDD
8-to-1 Analog MUX LVDEN 0 1 2 6 7 LVDL<2:0> Reference Voltage Generator
+ det LVDIF
FIGURE 11-2:
PLVD OPERATION
VDD PLVD Trip Point
LVDIF Set by Hardware Cleared by Software
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11.1 PLVD Operation 11.4 Stable Reference Indication
To setup the PLVD for operation, the following steps must be taken: * Enable the module by setting the LVDEN bit of the LVDCON register. * Configure the trip point by setting the LVDL<2:0> bits of the LVDCON register. * Wait for the reference voltage to become stable. Refer to Section 11.4 "Stable Reference Indication". * Clear the LVDIF bit of the PIR2 register. The LVDIF bit will be set when VDD falls below the PLVD trip point. The LVDIF bit remains set until cleared by software. Refer to Figure 11-2. When the PLVD module is enabled, the reference voltage must be allowed to stabilize before the PLVD will provide a valid result. Refer to Section 19.0 "Electrical Specifications", Table 19-13, for the stabilization time. When the HFINTOSC is running, the IRVST bit of the LVDCON register indicates the stability of the voltage reference. The voltage reference is stable when the IRVST bit is set.
11.5
Operation During Sleep
11.2
Programmable Trip Point
The PLVD trip point is selectable from one of eight voltage levels. The LVDL bits of the LVDCON register select the trip point. Refer to Register 11-1 for the available PLVD trip points.
To wake from Sleep, set the LVDIE bit of the PIE2 register and the PEIE bit of the INTCON register. When the LVDIE and PEIE bits are set, the device will wake from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine upon completion of the first instruction after waking from Sleep.
11.3
Interrupt on Falling VDD
When VDD falls below the PLVD trip point, the falling edge detector will set the LVDIF bit. See Figure 11-2. An interrupt will be generated if the following bits are also set: * GIE and PEIE bits of the INTCON register * LVDIE bit of the PIE2 register The LVDIF bit must be cleared by software. An interrupt can be generated from a simulated PLVD event when the LVDIF bit is set by software.
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REGISTER 11-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
LVDCON: LOW-VOLTAGE DETECT CONTROL REGISTER
U-0 -- R-0 IRVST
(1)
R/W-0 LVDEN
U-0 --
R/W-1 LVDL2
R/W-0 LVDL1
R/W-0 LVDL0 bit 0
Unimplemented: Read as `0' IRVST: Internal Reference Voltage Stable Status Flag bit(1) 1 = Indicates that the PLVD is stable and PLVD interrupt is reliable 0 = Indicates that the PLVD is not stable and PLVD interrupt must not be enabled LVDEN: Low-Voltage Detect Module Enable bit 1 = Enables PLVD Module, powers up PLVD circuit and supporting reference circuitry 0 = Disables PLVD Module, powers down PLVD circuit and supporting reference circuitry Unimplemented: Read as `0' LVDL<2:0>: Low-Voltage Detection Level bits (nominal values)(3) 111 = 4.5V 110 = 4.2V 101 = 4.0V 100 = 2.3V (default) 011 = 2.2V 010 = 2.1V 001 = 2.0V(2) 000 = Reserved The IRVST bit is usable only when the HFINTOSC is running. Not tested and below minimum operating conditions. See Section 19.0 "Electrical Specifications".
bit 4
bit 3 bit 2-0
Note 1: 2: 3:
TABLE 11-1:
Name INTCON LVDCON PIE2 PIR2
REGISTERS ASSOCIATED WITH PROGRAMMABLE LOW-VOLTAGE DETECT
Bit 6 PEIE -- C2IE C2IF Bit 5 T0IE IRVST C1IE C1IF Bit 4 INTE LVDEN LCDIE LCDIF Bit 3 RBIE -- -- -- Bit 2 T0IF LVDL2 LVDIE LVDIF Bit 1 INTF LVDL1 -- -- Bit 0 RBIF Value on POR, BOR Value on all other Resets
Bit 7 GIE -- OSFIE OSFIF
0000 000x 0000 000x
LVDL0 --00 -100 --00 -100 CCP2IE 0000 -0-0 0000 -0-0 CCP2IF 0000 -0-0 0000 -0-0
Legend: x = unknown, - = unimplemented read as `0'. Shaded cells are not used by the PLVD module.
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12.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE
The ADC voltage reference is software selectable to be either internally generated or externally supplied. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. Figure 12-1 shows the block diagram of the ADC.
The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESL and ADRESH).
FIGURE 12-1:
ADC BLOCK DIAGRAM
VDD VCFG0 = 0 VREF+ VCFG0 = 1
RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3 RA5/AN4 RE0/AN5(1) RE1/AN6(1) RE2/AN7(1) CHS
000 001 010 011 100 101 110 111 ADFM
ADC GO/DONE
10 0 = Left Justify 1 = Right Justify 10
ADON VSS VCFG1 = 0
ADRESH
ADRESL
VREFNote 1:
VCFG1 = 1
These channels are only available on PIC16F914/917 and PIC16F946 devices.
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12.1 ADC Configuration
12.1.3
ADC VOLTAGE REFERENCE
When configuring and using the ADC the following functions must be considered: * * * * * * Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Results formatting
The VCFG bits of the ADCON0 register provide independent control of the positive and negative voltage references. The positive voltage reference can be either VDD or an external voltage source. Likewise, the negative voltage reference can be either VSS or an external voltage source.
12.1.4
CONVERSION CLOCK
12.1.1
PORT CONFIGURATION
The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: * * * * * * * FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (dedicated internal oscillator)
The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. See the corresponding Port section for more information. Note: Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current.
12.1.2
CHANNEL SELECTION
The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section 12.2 "ADC Operation" for more information.
The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11 TAD periods as shown in Figure 12-3. For correct conversion, the appropriate TAD specification must be met. See A/D conversion requirements in Section 19.0 "Electrical Specifications" for more information. Table 12-1 gives examples of appropriate ADC clock selections. Note: Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result.
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TABLE 12-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)
Device Frequency (FOSC) 20 MHz 100 ns 400 ns 800 ns
(2)
ADC Clock Period (TAD) ADC Clock Source FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC Legend: Note 1: 2: 3: 4: ADCS<2:0> 000 100 001 101 010 110 x11
8 MHz 250 ns 1.0 s
(2)
4 MHz 500 ns
(2)
1 MHz 2.0 s 4.0 s 8.0 s(3) 16.0 s(3) 32.0 s(3) 64.0 s(3) 2-6 s(1,4)
200 ns(2)
(2) (2)
500 ns(2)
(2)
1.0 s(2) 2.0 s 4.0 s 8.0 s(3) 16.0 s
(3)
2.0 s 4.0 s 8.0 s
(3)
1.6 s 3.2 s 2-6 s(1,4)
2-6 s(1,4)
2-6 s(1,4)
Shaded cells are outside of recommended range. The FRC source has a typical TAD time of 4 s for VDD > 3.0V. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the conversion will be performed during Sleep.
FIGURE 12-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion Starts Holding Capacitor is Disconnected from Analog Input (typically 100 ns) Set GO/DONE bit ADRESH and ADRESL registers are loaded, GO bit is cleared, ADIF bit is set, Holding capacitor is connected to analog input
12.1.5
INTERRUPTS
The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC interrupt flag is the ADIF bit in the PIR1 register. The ADC interrupt enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. Note: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled.
This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the global interrupt must be disabled. If the global interrupt is enabled, execution will switch to the Interrupt Service Routine. Please see Section 12.1.5 "Interrupts" for more information.
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12.1.6 RESULT FORMATTING
The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON0 register controls the output format. Figure 12-4 shows the two output formats.
FIGURE 12-3:
10-BIT A/D CONVERSION RESULT FORMAT
ADRESH ADRESL LSB bit 0 10-bit A/D Result bit 7 bit 0 Unimplemented: Read as `0' LSB bit 0 bit 7 10-bit A/D Result bit 0
(ADFM = 0)
MSB bit 7
(ADFM = 1) bit 7 Unimplemented: Read as `0'
MSB
12.2
12.2.1
ADC Operation
STARTING A CONVERSION
12.2.4
ADC OPERATION DURING SLEEP
To enable the ADC module, the ADON bit of the ADCON0 register must be set to a `1'. Setting the GO/DONE bit of the ADCON0 register to a `1' will start the Analog-to-Digital conversion. Note: The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 12.2.6 "A/D Conversion Procedure".
The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set.
12.2.2
COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will: * Clear the GO/DONE bit * Set the ADIF flag bit * Update the ADRESH:ADRESL registers with new conversion result
12.2.5
SPECIAL EVENT TRIGGER
12.2.3
TERMINATING A CONVERSION
If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The ADRESH:ADRESL registers will not be updated with the partially complete Analog-to-Digital conversion sample. Instead, the ADRESH:ADRESL register pair will retain the value of the previous conversion. Additionally, a 2 TAD delay is required before another acquisition can be initiated. Following this delay, an input acquisition is automatically started on the selected channel. Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated.
The CCP Special Event Trigger allows periodic ADC measurements without software intervention. When this trigger occurs, the GO/DONE bit is set by hardware and the Timer1 counter resets to zero. Using the Special Event Trigger does not assure proper ADC timing. It is the user's responsibility to ensure that the ADC timing requirements are met. See Section 15.0 "Capture/Compare/PWM (CCP) Module" for more information.
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12.2.6 A/D CONVERSION PROCEDURE EXAMPLE 12-1: A/D CONVERSION
This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. Configure Port: * Disable pin output driver (See TRIS register) * Configure pin as analog Configure the ADC module: * Select ADC conversion clock * Configure voltage reference * Select ADC input channel * Select result format * Turn on ADC module Configure ADC interrupt (optional): * Clear ADC interrupt flag * Enable ADC interrupt * Enable peripheral interrupt * Enable global interrupt(1) Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: * Polling the GO/DONE bit * Waiting for the ADC interrupt (interrupts enabled) Read ADC Result Clear the ADC interrupt flag (required if interrupt is enabled). Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: See Section 12.3 "A/D Acquisition Requirements".
;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and AN0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL ADCON1 ; MOVLW B'01110000' ;ADC Frc clock MOVWF ADCON1 ; BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input BANKSEL ANSEL ; BSF ANSEL,0 ;Set RA0 to analog BANKSEL ADCON0 ; MOVLW B'10000001' ;Right justify, MOVWF ADCON0 ;Vdd Vref, AN0, On CALL SampleTime ;Acquisiton delay BSF ADCON0,GO ;Start conversion BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space
2.
3.
4. 5. 6.
7. 8.
12.2.7
ADC REGISTER DEFINITIONS
The following registers are used to control the operation of the ADC.
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REGISTER 12-1:
R/W-0 ADFM bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADCON0: A/D CONTROL REGISTER 0
R/W-0 R/W-0 VCFG0 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE R/W-0 ADON bit 0
VCFG1
ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified VCFG1: Voltage Reference bit 1 = VREF- pin 0 = VSS VCFG0: Voltage Reference bit 1 = VREF+ pin 0 = VSS CHS<2:0>: Analog Channel Select bits 000 = AN0 001 = AN1 010 = AN2 011 = AN3 100 = AN4 101 = AN5(1) 110 = AN6(1) 111 = AN7(1) GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Not available on 28-pin devices.
bit 6
bit 5
bit 4-2
bit 1
bit 0
Note 1:
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REGISTER 12-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADCON1: A/D CONTROL REGISTER 1
R/W-0 R/W-0 ADCS1 R/W-0 ADCS0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
ADCS2
Unimplemented: Read as `0' ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max.) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 Unimplemented: Read as `0'
bit 3-0
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REGISTER 12-3:
R/W-x ADRES9 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x R/W-x ADRES7 R/W-x ADRES6 R/W-x ADRES5 R/W-x ADRES4 R/W-x ADRES3 R/W-x ADRES2 bit 0
ADRES8
ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result
REGISTER 12-4:
R/W-x ADRES1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x R/W-x -- R/W-x -- R/W-x -- R/W-x -- R/W-x -- R/W-x -- bit 0
ADRES0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result Reserved: Do not use.
REGISTER 12-5:
R/W-x -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-2 bit 1-0
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x -- R/W-x -- R/W-x -- R/W-x -- R/W-x -- R/W-x ADRES9 R/W-x ADRES8 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Reserved: Do not use. ADRES<9:8>: ADC Result Register bits Upper 2 bits of 10-bit conversion result
REGISTER 12-6:
R/W-x ADRES7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x R/W-x ADRES5 R/W-x ADRES4 R/W-x ADRES3 R/W-x ADRES2 R/W-x ADRES1 R/W-x ADRES0 bit 0
ADRES6
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result
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12.3 A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 12-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 12-4. The maximum recommended impedance for analog sources is 10 k. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 12-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution.
EQUATION 12-1: Assumptions:
ACQUISITION TIME EXAMPLE Temperature = 50C and external impedance of 10k 5.0V VDD
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF = 2s + TC + [ ( Temperature - 25C ) ( 0.05s/C ) ] The value for TC can be approximated with the following equations:
1 VAPPLIED 1 - -------------------------- = VCHOLD n+1 (2 )-1
--------- RC VAPPLIED 1 - e = VCHOLD - Tc - TC
;[1] VCHOLD charged to within 1/2 lsb
;[2] VCHOLD charge response to VAPPLIED
-------- 1 RC VAPPLIED 1 - e = VAPPLIED 1 - -------------------------- ;combining [1] and [2] n+1 (2 )-1
Note: Where n = number of bits of the ADC. Solving for TC:
TC = - CHOLD ( RIC + RSS + RS ) ln(1/2047) = - 10pF ( 1k + 7k + 10k ) ln(0.0004885) = 1.37 s
Therefore: TACQ = 2S + 1.37S + [ ( 50C- 25C ) ( 0.05S/C ) ] = 4.67S
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification.
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FIGURE 12-4: ANALOG INPUT MODEL
VDD Rs VA ANx CPIN 5 pF VT = 0.6V RIC 1k I LEAKAGE(1) Sampling Switch SS Rss CHOLD = 10 pF VSS/VREF-
VT = 0.6V
Legend: CPIN = Input Capacitance = Threshold Voltage VT I LEAKAGE = Leakage current at the pin due to various junctions = Interconnect Resistance RIC SS = Sampling Switch CHOLD = Sample/Hold Capacitance Note 1: See Section 19.0 "Electrical Specifications".
6V 5V VDD 4V 3V 2V
RSS
5 6 7 8 9 10 11 Sampling Switch (k)
FIGURE 12-5:
ADC TRANSFER FUNCTION
Full-Scale Range
3FFh 3FEh 3FDh ADC Output Code 3FCh 3FBh Full-Scale Transition 1 LSB ideal
004h 003h 002h 001h 000h 1 LSB ideal
Analog Input Voltage
VSS/VREF-
Zero-Scale Transition
VDD/VREF+
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TABLE 12-2:
Name ADCON0 ADCON1 ANSEL ADRESH ADRESL INTCON LCDCON LCDSE0 LCDSE1 LCDSE2(1) PIE1 PIR1 PORTA PORTB PORTE TRISA TRISB TRISE Legend: Bit 7 ADFM -- ANS7
SUMMARY OF ASSOCIATED ADC REGISTERS
Bit 6 VCFG1 ADCS2 ANS6 Bit 5 VCFG0 ADCS1 ANS5 Bit 4 CHS2 ADCS0 ANS4 Bit 3 CHS1 -- ANS3 Bit 2 CHS0 -- ANS2 Bit 1 GO/DONE -- ANS1 Bit 0 ADON -- ANS0 Value on POR, BOR 0000 0000 -000 ---1111 1111 xxxx xxxx xxxx xxxx INTE VLCDEN SE4 SE12 SE20 TXIE TXIF RA4 RB4 RE4 TRISA4 TRISB4 TRISE4 RBIE CS1 SE3 SE11 SE19 SSPIE SSPIF RA3 RB3 RE3 TRISA3 TRISB3 TRISE3 T0IF CS0 SE2 SE10 SE18 CCP1IE CCP1IF RA2 RB2 RE2 TRISA2 TRISB2 TRISE2 INTF LMUX1 SE1 SE9 SE17 TMR2IE TMR2IF RA1 RB1 RE1 TRISA1 TRISB1 TRISE1 RBIF LMUX0 SE0 SE8 SE16 TMR1IE TMR1IF RA0 RB0 RE0 TRISA0 TRISB0 TRISE0 0000 000x 0001 0011 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx 1111 1111 1111 ---1111 1111 Value on all other Resets 0000 0000 -000 ---1111 1111 uuuu uuuu uuuu uuuu 0000 000x 0001 0011 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu 1111 1111 1111 ---1111 1111
A/D Result Register High Byte A/D Result Register Low Byte GIE LCDEN SE7 SE15 SE23 EEIE EEIF RA7 RB7 RE7 TRISA7 TRISB7 TRISE7 PEIE SLPEN SE6 SE14 SE22 ADIE ADIF RA6 RB6 RE6 TRISA6 TRISB6 TRISE6 T0IE WERR SE5 SE13 SE21 RCIE RCIF RA5 RB5 RE5 TRISA5 TRISB5 TRISE5
x = unknown, u = unchanged, -- = unimplemented read as `0'. Shaded cells are not used for ADC module.
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13.0 DATA EEPROM AND FLASH PROGRAM MEMORY CONTROL
13.1 EEADRL and EEADRH Registers
The EEADRL and EEADRH registers can address up to a maximum of 256 bytes of data EEPROM or up to a maximum of 8K words of program Flash. When selecting a program address value, the MSB of the address is written to the EEADRH register and the LSB is written to the EEADRL register. When selecting a data address value, only the LSB of the address is written to the EEADRL register.
Data EEPROM memory is readable and writable and the Flash program memory is readable during normal operation (full VDD range). These memories are not directly mapped in the register file space. Instead, they are indirectly addressed through the Special Function Registers. There are six SFRs used to access these memories: * * * * * * EECON1 EECON2 EEDATL EEDATH EEADRL EEADRH
13.1.1
EECON1 AND EECON2 REGISTERS
EECON1 is the control register for EE memory accesses. Control bit EEPGD determines if the access will be a program or data memory access. When clear, as it is when reset, any subsequent operations will operate on the data memory. When set, any subsequent operations will operate on the program memory. Program memory can only be read. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation to data EEPROM. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a MCLR or a WDT Time-out Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit. The Data and Address registers will be cleared on the Reset. User code can then run an appropriate recovery routine. Interrupt flag bit EEIF of the PIR1 register is set when write is complete. It must be cleared in the software. EECON2 is not a physical register. Reading EECON2 will read all `0's. The EECON2 register is used exclusively in the data EEPROM write sequence.
When interfacing the data memory block, EEDATL holds the 8-bit data for read/write, and EEADRL holds the address of the EE data location being accessed. This device has 256 bytes of data EEPROM with an address range from 00h to FFh. When interfacing the program memory block, the EEDATL and EEDATH registers form a 2-byte word that holds the 14-bit data for read, and the EEADRL and EEADRH registers form a 2-byte word that holds the 13-bit address of the EEPROM location being accessed. This family of devices has 4K and 8K words of program Flash with an address range from 0h-0FFFh and 0h-1FFFh. The program memory allows one word reads. The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations. When the device is code-protected, the CPU may continue to read and write the data EEPROM memory and read the program memory. When code-protected, the device programmer can no longer access data or program memory.
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REGISTER 13-1:
R/W-0 EEDATL7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
EEDATL: EEPROM/PROGRAM MEMORY DATA LOW BYTE REGISTER
R/W-0 R/W-0 EEDATL5 R/W-0 EEDATL4 R/W-0 EEDATL3 R/W-0 EEDATL2 R/W-0 EEDATL1 R/W-0 EEDATL0 bit 0
EEDATL6
EEDATL<7:0>: Byte value to Write to or Read from data EEPROM bits or to Read from program memory
REGISTER 13-2:
R/W-0 EEADRL7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
EEADRL: EEPROM/PROGRAM MEMORY ADDRESS LOW BYTE REGISTER
R/W-0 R/W-0 EEADRL5 R/W-0 EEADRL4 R/W-0 EEADRL3 R/W-0 EEADRL2 R/W-0 EEADRL1 R/W-0 EEADRL0 bit 0
EEADRL6
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
EEADRL<7:0>: Specifies one of 256 locations for EEPROM Read/Write operation bits or low address byte for program memory reads
REGISTER 13-3:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
EEDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER
U-0 -- R/W-0 EEDATH5 R/W-0 EEDATH4 R/W-0 EEDATH3 R/W-0 EEDATH2 R/W-0 EEDATH1 R/W-0 EEDATH0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' EEDATH<5:0>: Byte value to Read from program memory
REGISTER 13-4:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0
EEADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER
U-0 -- U-0 -- R/W-0 EEDATH4 R/W-0 EEDATH3 R/W-0 EEDATH2 R/W-0 EEDATH1 R/W-0 EEDATH0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' EEADRH<4:0>: Specifies the high address byte for program memory reads
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REGISTER 13-5:
R/W-x EEPGD bit 7 Legend: S = Bit can only be set R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
EECON1: EEPROM CONTROL REGISTER
U-0 -- U-0 -- U-0 -- R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0
EEPGD: Program/Data EEPROM Select bit 1 = Accesses program memory 0 = Accesses data memory Unimplemented: Read as `0' WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during normal operation or BOR Reset) 0 = The write operation completed WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM WR: Write Control bit EEPGD = 1: This bit is ignored EEPGD = 0: 1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only be set, not cleared, in software.) 0 = Write cycle to the data EEPROM is complete RD: Read Control bit 1 = Initiates a memory read (the RD is cleared in hardware and can only be set, not cleared, in software.) 0 = Does not initiate a memory read
bit 6-4 bit 3
bit 2
bit 1
bit 0
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13.1.2 READING THE DATA EEPROM MEMORY
The steps to write to EEPROM data memory are: 1. If step 10 is not implemented, check the WR bit to see if a write is in progress. 2. Write the address to EEADRL. Make sure that the address is not larger than the memory size of the device. 3. Write the 8-bit data value to be programmed in the EEDATL register. 4. Clear the EEPGD bit to point to EEPROM data memory. 5. Set the WREN bit to enable program operations. 6. Disable interrupts (if enabled). 7. Execute the special five instruction sequence: * Write 55h to EECON2 in two steps (first to W, then to EECON2) * Write AAh to EECON2 in two steps (first to W, then to EECON2) * Set the WR bit 8. Enable interrupts (if using interrupts). 9. Clear the WREN bit to disable program operations. 10. At the completion of the write cycle, the WR bit is cleared and the EEIF interrupt flag bit is set. (EEIF must be cleared by firmware.) If step 1 is not implemented, then firmware should check for EEIF to be set, or WR to clear, to indicate the end of the program cycle. To read a data memory location, the user must write the address to the EEADRL register, clear the EEPGD control bit, and then set control bit RD of the EECON1 register. The data is available in the very next cycle, in the EEDATL register; therefore, it can be read in the next instruction. EEDATL will hold this value until another read or until it is written to by the user (during a write operation).
EXAMPLE 13-1:
BANKSEL MOVF MOVWF BANKSEL BCF
DATA EEPROM READ
; ;Data Memory ;Address to read ; ;Point to Data ;memory ;EE Read ; ;W = EEPROM Data
EEADRL DATA_EE_ADDR,W EEADRL EECON1 EECON1,EEPGD
BSF EECON1,RD BANKSEL EEDATL MOVF EEDATL,W
13.1.3
WRITING TO THE DATA EEPROM MEMORY
To write an EEPROM data location, the user must first write the address to the EEADRL register and the data to the EEDATL register. Then the user must follow a specific sequence to initiate the write for each byte. The write will not initiate if the sequence described below is not followed exactly (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. Interrupts should be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware. After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software.
EXAMPLE 13-2:
BANKSEL BTFSC GOTO BANKSEL MOVF MOVWF MOVF MOVWF BANKSEL BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF
DATA EEPROM WRITE
EECON1 ; EECON1,WR ;Wait for write $-1 ;to complete EEADRL ; DATA_EE_ADDR,W ;Data Memory EEADRL ;Address to write DATA_EE_DATA,W ;Data Memory Value EEDATL ;to write EECON1 ; EECON1,EEPGD ;Point to DATA ;memory EECON1,WREN ;Enable writes INTCON,GIE 55h EECON2 AAh EECON2 EECON1,WR INTCON,GIE EECON1,WREN ;Disable INTs. ; ;Write 55h ; ;Write AAh ;Set WR bit to ;begin write ;Enable INTs. ;Disable writes
Required Sequence
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13.1.4 READING THE FLASH PROGRAM MEMORY
To read a program memory location, the user must write two bytes of the address to the EEADRL and EEADRH registers, set the EEPGD control bit, and then set control bit RD of the EECON1 register. Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the "BSF EECON1,RD" instruction to be ignored. The data is available in the very next cycle, in the EEDATL and EEDATH registers; therefore, it can be read as two bytes in the following instructions. EEDATL and EEDATH registers will hold this value until another read or until it is written to by the user (during a write operation). Note 1: The two instructions following a program memory read are required to be NOP's. This prevents the user from executing a two-cycle instruction on the next instruction after the RD bit is set. 2: If the WR bit is set when EEPGD = 1, the WR bit will be immediately reset to `0' and no operation will take place.
EXAMPLE 13-3:
BANKSEL MOVLW MOVWF MOVLW MOVWF BANKSEL BSF BSF ; NOP NOP ; BANKSEL MOVF MOVWF MOVF MOVWF
FLASH PROGRAM READ
EEADRL ; MS_PROG_EE_ADDR; EEADRH ;MS Byte of Program Address to read LS_PROG_EE_ADDR; EEADRL ;LS Byte of Program Address to read EECON1 ; EECON1, EEPGD ;Point to PROGRAM memory EECON1, RD ;EE Read
Required Sequence
;Any instructions here are ignored as program ;memory is read in second cycle after BSF EEDATL EEDATL, W DATAL EEDATH, W DATAH ; ;W = LS Byte of EEPROM Data program ; ;W = MS Byte of EEPROM Data program ;
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FIGURE 13-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash ADDR
PC
PC + 1
EEADRH,EEADRL
PPC+3 C+3
PC + 4
PC + 5
Flash Data
INSTR (PC)
INSTR (PC + 1)
EEDATH,EEDATL
INSTR (PC + 3)
INSTR (PC + 4)
INSTR(PC - 1) executed here
BSF EECON1,RD executed here
INSTR(PC + 1) executed here
Forced NOP executed here
INSTR(PC + 3) executed here
INSTR(PC + 4) executed here
RD bit
EEDATH EEDATL register
EERHLT
TABLE 13-1:
Name INTCON PIE1 PIR1 EEADRH EEADRL EECON1 EECON2 EEDATH EEDATL Legend: Bit 7 GIE EEIE EEIF --
SUMMARY OF ASSOCIATED REGISTERS WITH DATA EEPROM
Bit 6 PEIE ADIE ADIF -- EEADRL6 -- -- EEDATL6 Bit 5 T0IE RCIE RCIF -- EEADRL5 -- EEDATH5 EEDATL5 Bit 4 INTE TXIE TXIF EEADRL4 -- EEDATH4 EEDATL4 Bit 3 RBIE SSPIE SSPIF EEADRL3 WRERR EEDATH3 EEDATL3 Bit 2 T0IF CCP1IE CCP1IF EEADRL2 WREN EEDATH2 EEDATL2 Bit 1 INTF TMR2IE TMR2IF EEADRL1 WR EEDATH1 EEDATL1 Bit 0 RBIF TMR1IE TMR1IF EEADRL0 RD EEDATH0 EEDATL0 Value on POR, BOR 0000 000x 0000 0000 0000 0000 ---0 0000 0000 0000 0--- x000 ---- -----00 0000 0000 0000 Value on all other Resets 0000 000x 0000 0000 0000 0000 ---0 0000 0000 0000 ---- q000 ---- -----00 0000 0000 0000
EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0
EEADRL7 EEPGD -- EEDATL7
EEPROM Control Register 2 (not a physical register)
x = unknown, u = unchanged, - = unimplemented read as `0', q = value depends upon condition. Shaded cells are not used by data EEPROM module.
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14.0 SSP MODULE OVERVIEW
FIGURE 14-1:
The Synchronous Serial Port (SSP) module is a serial interface used to communicate with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2CTM) Refer to Application Note AN578, "Use of the SSP Module in the Multi-Master Environment" (DS00578).
SSPSR Reg SDI/SDA SDO bit 0 Shift Clock
SSP BLOCK DIAGRAM (SPI MODE)
Internal Data Bus Read SSPBUF Reg Write
14.1
SPI Mode
This section contains register definitions and operational characteristics of the SPI module. The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used: * Serial Data Out (SDO) * Serial Data In (SDI) * Serial Clock (SCK) Additionally, a fourth pin may be used when in a Slave mode of operation: * Slave Select (SS) Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPM<3:0> bits of the SSPCON register = 0100), the SPI module will reset if the SS pin is set to VDD. 2: If the SPI is used in Slave mode with CKE = 1, then the SS pin control must be enabled. 3: When the SPI is in Slave mode with SS pin control enabled (SSPM<3:0> bits of the SSPCON register = 0100), the state of the SS pin can affect the state read back from the TRISC<4> bit. The peripheral OE signal from the SSP module into PORTC controls the state that is read back from the TRISC<4> bit (see Section 19.0 "Electrical Specifications" for information on PORTC). If read-write-modify instructions, such as BSF, are performed on the TRISC register while the SS pin is high, this will cause the TRISC<4> bit to be set, thus disabling the SDO output.
Peripheral OE
SS Control Enable SS Edge Select 2 Clock Select SSPM<3:0> 4 Edge Select SCK/ SCL TRISC<6> TMR2 Output 2 Prescaler TCY 4, 16, 64
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REGISTER 14-1:
R/W-0 SMP bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
SSPSTAT: SYNC SERIAL PORT STATUS REGISTER
R/W-0 CKE R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit 0
SMP: SPI Data Input Sample Phase bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Microwire) SPI Slave mode: SMP must be cleared when SPI is used in Slave mode I2 CTM mode: This bit must be maintained clear CKE: SPI Clock Edge Select bit SPI mode, CKP = 0: 1 = Data stable on rising edge of SCK (Microwire alternate) 0 = Data stable on falling edge of SCK SPI mode, CKP = 1: 1 = Data stable on falling edge of SCK (Microwire default) 0 = Data stable on rising edge of SCK I2 C mode: This bit must be maintained clear D/A: DATA/ADDRESS bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: Stop bit (I2C mode only) This bit is cleared when the SSP module is disabled, or when the Start bit is detected last. SSPEN is cleared. 1 = Indicates that a Stop bit has been detected last (this bit is `0' on Reset) 0 = Stop bit was not detected last S: Start bit (I2C mode only) This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last. SSPEN is cleared. 1 = Indicates that a Start bit has been detected last (this bit is `0' on Reset) 0 = Start bit was not detected last R/W: READ/WRITE bit Information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or ACK bit. 1 = Read 0 = Write UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2 C mode only): 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 14-2:
R/W-0 WCOL bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
SSPCON: SYNC SERIAL PORT CONTROL REGISTER
R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3(2) R/W-0 SSPM2(2) R/W-0 SSPM1(2) R/W-0 SSPM0(2) bit 0
WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision SSPOV: Receive Overflow Indicator bit In SPI mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I2 CTM mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don't care" in Transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow
bit 6
bit 5
SSPEN: Synchronous Serial Port Enable bit In SPI mode: 1 = Enables serial port and configures SCK, SDO and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In both modes, when enabled, these pins must be properly configured as input or output.
bit 4
CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level (Microwire default) 0 = Idle state for clock is a low level (Microwire alternate) In I2 C mode: SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
bit 3-0
SSPM<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = Reserved 1001 = Reserved 1010 = Reserved 1011 = I2C Firmware Controlled Master mode (slave IDLE) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
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14.2 Operation
When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: * * * * Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Data Input Sample Phase (middle or end of data output time) * Clock Edge (output data on rising/falling edge of SCK) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only) The SSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR until the received data is ready. Once the eight bits of data have been received, that byte is moved to the SSPBUF register. Then, the Buffer Full Status bit BF of the SSPSTAT register, and the interrupt flag bit SSPIF, are set. Any write to the SSPBUF register during transmission/reception of data will be ignored and the Write Collision Detect bit, WCOL of the SSPCON register, will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. Buffer Full bit BF of the SSPSTAT register indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the SSP interrupt is used to determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 14-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the SSP STATUS register (SSPSTAT) indicates the various status conditions.
EXAMPLE 14-1:
LOOP BANKSEL BTFSS GOTO BANKSEL MOVF MOVWF MOVF MOVWF
LOADING THE SSPBUF (SSPSR) REGISTER
SSPSTAT SSPSTAT, BF LOOP SSPBUF SSPBUF, W RXDATA TXDATA, W SSPBUF ; ;Has data been received(transmit complete)? ;No ; ;WREG reg = contents of SSPBUF ;Save in user RAM, if data is meaningful ;W reg = contents of TXDATA ;New data to xmit
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14.3 Enabling SPI I/O 14.4 Typical Connection
To enable the serial port, SSP Enable bit SSPEN of the SSPCON register must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, their data direction bits (in the TRISA and TRISC registers) should be set as follows: TRISC<7> bit must be set SDI is automatically controlled by the SPI module SDO must have TRISC<4> bit cleared SCK (Master mode) must have TRISC<6> bit cleared * SCK (Slave mode) must have TRISC<6> bit set * If enabled, SS must have TRISA<5> bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRISA and TRISC) registers to the opposite value. * * * * Figure 14-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock. Both processors should be programmed to the same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission: * Master sends data - Slave sends dummy data * Master sends data - Slave sends data * Master sends dummy data - Slave sends data
FIGURE 14-2:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM<3:0> = 00xxb SDO Serial Input Buffer (SSPBUF) SDI
SPI Slave SSPM<3:0> = 010xb
Serial Input Buffer (SSPBUF)
Shift Register (SSPSR) MSb LSb
SDI
SDO MSb
Shift Register (SSPSR) LSb
SCK Processor 1
Serial Clock
SCK Processor 2
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14.5 Master Mode
The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 14-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal received byte (interrupts and Status bits appropriately set). This could be useful in receiver applications as a Line Activity Monitor mode. The clock polarity is selected by appropriately programming the CKP bit of the SSPCON register. This then, would give waveforms for SPI communication as shown in Figure 14-3, Figure 14-5 and Figure 14-6, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: * * * * FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2
This allows a maximum data rate (at 20 MHz) of 5 Mbps. Figure 14-3 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown.
FIGURE 14-3:
Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) SDO (CKE = 1) SDI (SMP = 0) Input Sample (SMP = 0) SDI (SMP = 1) Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF
SPI MODE WAVEFORM (MASTER MODE)
4 Clock Modes
bit 7 bit 7
bit 6 bit 6
bit 5 bit 5
bit 4 bit 4
bit 3 bit 3
bit 2 bit 2
bit 1 bit 1
bit 0 bit 0
bit 7
bit 0
bit 7
bit 0
Next Q4 Cycle after Q2
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14.6 Slave Mode
In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. When a byte is received, the device will wake-up from Sleep. even if in the middle of a transmitted byte, and becomes a floating output. External pull-up/pull-down resistors may be desirable, depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. 2: If the SPI is used in Slave Mode with CKE set, then the SS pin control must be enabled. When the SPI module resets, the bit counter is forced to 0. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. To emulate two-wire communication, the SDO pin can be connected to the SDI pin. When the SPI needs to operate as a receiver, the SDO pin can be configured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function) since it cannot create a bus conflict.
14.7
Slave Select Synchronization
The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100). The pin must not be driven low for the SS pin to function as an input. The data latch must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven,
FIGURE 14-4:
SS
SLAVE SYNCHRONIZATION WAVEFORM
SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0)
Write to SSPBUF
SDO
bit 7
bit 6
bit 7
bit 0
SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF
bit 0 bit 7 bit 7
Next Q4 Cycle after Q2
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FIGURE 14-5:
SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
bit 7
bit 0
Next Q4 Cycle after Q2
FIGURE 14-6:
SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 0
Next Q4 Cycle after Q2
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14.8 Sleep Operation 14.10 Bus Mode Compatibility
Table 14-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits. In Master mode, all module clocks are halted and the transmission/reception will remain in that state until the device wakes from Sleep. After the device returns to Normal mode, the module will continue to transmit/receive data. In Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the SSP interrupt flag bit will be set and if enabled, will wake the device from Sleep.
TABLE 14-1:
SPI BUS MODES
Control Bits State CKP 0 0 1 1 CKE 1 0 1 0
Standard SPI Mode Terminology 0, 0 0, 1 1, 0 1, 1
14.9
Effects of a Reset
A Reset disables the SSP module and terminates the current transfer.
There is also a SMP bit which controls when the data is sampled.
TABLE 14-2:
Name INTCON LCDCON LCDSE0 LCDSE1 PIE1 PIR1 RCSTA SSPBUF SSPCON SSPSTAT TRISA TRISC Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Bit 6 PEIE SLPEN SE6 SE14 ADIE ADIF RX9 SSPOV CKE TRISA6 TRISC6 Bit 5 T0IE WERR SE5 SE13 RCIE RCIF SREN SSPEN D/A TRISA5 TRISC5 Bit 4 INTE VLCDEN SE4 SE12 TXIE TXIF CREN CKP P TRISA4 TRISC4 Bit 3 RBIE CS1 SE3 SE11 SSPIE SSPIF ADDEN SSPM3 S TRISA3 TRISC3 Bit 2 T0IF CS0 SE2 SE10 CCP1IE CCP1IF FERR SSPM2 R/W TRISA2 TRISC2 Bit 1 INTF LMUX1 SE1 SE9 TMR2IE TMR2IF OERR SSPM1 UA TRISA1 TRISC1 Bit 0 RBIF LMUX0 SE0 SE8 TMR1IE TMR1IF RX9D SSPM0 BF TRISA0 TRISC0 Value on POR, BOR 0000 000x 0001 0011 0000 0000 0000 0000 0000 0000 0000 0000 0000 000x xxxx xxxx 0000 0000 0000 0000 1111 1111 1111 1111 Value on all other Resets 0000 000x 0001 0011 0000 0000 0000 0000 0000 0000 0000 0000 0000 000x uuuu uuuu 0000 0000 0000 0000 1111 1111 1111 1111
Bit 7 GIE LCDEN SE7 SE15 EEIE EEIF SPEN WCOL SMP TRISA7 TRISC7
Synchronous Serial Port Receive Buffer/Transmit Register
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the SSP in SPI mode.
(c) 2007 Microchip Technology Inc.
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14.11 SSP I2C Operation
The SSP module in I2C mode, fully implements all slave functions, except general call support, and provides interrupts on Start and Stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the Standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the RC6/TX/CK/SCK/SCL/SEG9 pin, which is the clock (SCL), and the RC7/RX/DT/SDI/SDA/SEG8 pin, which is the data (SDA). The SSP module functions are enabled by setting SSP enable bit SSPEN (SSPCON<5>). The SSPCON register allows control of the I2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I2C modes to be selected: I2C Slave mode (7-bit address) I2C Slave mode (10-bit address) I2C Slave mode (7-bit address), with Start and Stop bit interrupts enabled to support Firmware Master mode * I2C Slave mode (10-bit address), with Start and Stop bit interrupts enabled to support Firmware Master mode * I2C Start and Stop bit interrupts enabled to support Firmware Master mode; Slave is idle * * * Selection of any I2C mode with the SSPEN bit set forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits. Pull-up resistors must be provided externally to the SCL and SDA pins for proper operation of the I2C module.
FIGURE 14-7:
SSP BLOCK DIAGRAM (I2CTM MODE)
Internal Data Bus
Read SCK/ SCL Shift Clock SSPSR Reg SDI/ SDA MSb SSPBUF Reg
Write
14.12 Slave Mode
In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<7,6> are set). The SSP module will override the input state with the output data when required (slave-transmitter). When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse, and then load the SSPBUF register with the received value currently in the SSPSR register. There are certain conditions that will cause the SSP module not to give this ACK pulse. They include (either or both):
LSb Addr Match
Match Detect
SSPADD Reg Start and Stop bit Detect Set, Reset S, P bits (SSPSTAT Reg.)
a) b)
The SSP module has five registers for the I2C operation, which are listed below. * * * * SSP Control register (SSPCON) SSP STATUS register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) SSP Shift register (SSPSR) - Not directly accessible * SSP Address register (SSPADD)
The Buffer Full bit BF of the SSPSTAT register was set before the transfer was received. The overflow bit SSPOV of the SSPCON register was set before the transfer was received.
In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF of the PIR1 register is set. Table 14-3 shows the results of when a data transfer byte is received, given the status of bits BF and SSPOV. The shaded cells show the condition where user software did not properly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. For high and low times of the I2C specification, as well as the requirements of the SSP module, see Section 19.0 "Electrical Specifications".
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14.12.1 ADDRESSING
Once the SSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of register SSPADD <7:1>. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur: a) b) c) d) The SSPSR register value is loaded into the SSPBUF register. The buffer full bit, BF is set. An ACK pulse is generated. SSP interrupt flag bit, SSPIF of the PIR1 register is set (interrupt is generated if enabled) on the falling edge of the ninth SCL pulse. The sequence of events for 10-bit address is as follows, with steps 7-9 for slave-transmitter: 1. 2. Receive first (high) byte of address (bits SSPIF, BF and bit UA (SSPSTAT<1>) are set). Update the SSPADD register with second (low) byte of address (clears bit UA and releases the SCL line). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive second (low) byte of address (bits SSPIF, BF and UA are set). Update the SSPADD register with the first (high) byte of address; if match releases SCL line, this will clear bit UA. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive repeated Start condition. Receive first (high) byte of address (bits SSPIF and BF are set). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF.
3. 4. 5.
6. 7. 8. 9.
In 10-bit Address mode, two address bytes need to be received by the slave (Figure 14-8). The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal `1111 0 A9 A8 0', where A9 and A8 are the two MSbs of the address.
TABLE 14-3:
DATA TRANSFER RECEIVED BYTE ACTIONS
SSPSR SSPBUF Yes No No No Generate ACK Pulse Yes No No No Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes Yes
Status Bits as Data Transfer is Received BF 0 1 1 0 Note: SSPOV 0 0 1 1
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
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14.12.2 RECEPTION
When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. When the address byte overflow condition exists, then no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF of the SSPSTAT register is set, or bit SSPOV of the SSPCON register is set. This is an error condition due to the user's firmware. An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF of the PIR1 register must be cleared in software. The SSPSTAT register is used to determine the status of the byte.
FIGURE 14-8:
I2CTM WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
R/W = 0 Receiving Address ACK Receiving Data D7 D6 D5 D4 D3 D2 D1 D0 8 9 1 2 3 4 5 6 7 8 9 ACK Receiving Data ACK D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 P Bus Master terminates transfer
SDA SCL S
A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7
SSPIF (PIR1<3>)
Cleared in software
BF (SSPSTAT<0>)
SSPBUF register is read
SSPOV (SSPCON<6>) Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent.
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FIGURE 14-9:
Clock is held low until update of SSPADD has taken place Receive Second Byte of Address ACK A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Receive Data Byte ACK Receive Data Byte
(c) 2007 Microchip Technology Inc.
Clock is held low until update of SSPADD has taken place ACK D7 D6 D5 D4 D3 D2 D1 D0 6 4 6 1 5 6 7 1 2 3 4 5 7 8 2 7 1 2 3 8 9 8 9 9 3 4 5 6 7 8 9 P Bus master terminates transfer Cleared in software Cleared in software Cleared in software Dummy read of SSPBUF to clear BF flag SSPOV is set because SSPBUF is still full. ACK is not sent. Cleared by hardware when SSPADD is updated with low byte of address UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address
SDA
Receive First Byte of Address R/W = 0 ACK 1 1 1 1 0 A9 A8 0
SCL
S
1
2
3
4
5
SSPIF
(PIR1<3>)
Cleared in software
BF (SSPSTAT<0>)
SSPBUF is written with contents of SSPSR
SSPOV (SSPCON<6>)
UA (SSPSTAT<1>)
I2CTM SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS)
UA is set indicating that the SSPADD needs to be updated
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CKP
(CKP does not reset to `0' when SEN = 0)
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14.12.3 TRANSMISSION
When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit, and pin RC6/TX/CK/SCK/SCL/SEG9 is held low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then, pin RC6/TX/CK/SCK/SCL/SEG9 should be enabled by setting bit CKP of the SSPCON register. The master must monitor the SCL pin prior to asserting another clock pulse. The slave devices may be holding off the master by stretching the clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 14-10). An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse. As a slave-transmitter, the ACK pulse from the master receiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line was high (not ACK), then the data transfer is complete. When the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT register) and the slave then monitors for another occurrence of the Start bit. If the SDA line was low (ACK), the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC6/TX/CK/SCK/SCL/SEG9 should be enabled by setting bit CKP.
FIGURE 14-10:
I2CTM WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
Receiving Address R/W = 1 A1 ACK D7 D6 D5 D4 Transmitting Data D3 D2 D1 D0 ACK
SDA
A7
A6
A5
A4
A3
A2
SCL
S
1 2 Data in sampled
3
4
5
6
7
8
9
1 SCL held low while CPU responds to SSPIF
2
3
4
5
6
7
8
9
P
SSPIF (PIR1<3>) BF (SSPSTAT<0>)
Cleared in software
SSPBUF is written in software CKP (SSPCON<4>)
From SSP Interrupt Service Routine
Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set)
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FIGURE 14-11:
(c) 2007 Microchip Technology Inc.
6 4 6 1 5 6 7 1 2 3 4 5 7 8 2 3 7 8 9 1 2 3 8 9 9 4 5 6 7 8 9 P Bus master terminates transfer Cleared in software Cleared in software Cleared in software Dummy read of SSPBUF to clear BF flag SSPOV is set because SSPBUF is still full. ACK is not sent. Cleared by hardware when SSPADD is updated with low byte of address UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address
SDA
Clock is held low until Clock is held low until update of SSPADD has update of SSPADD has taken place taken place Receive Second Byte of Address Receive First Byte of Address R/W = 0 Receive Data Byte Receive Data Byte ACK ACK ACK ACK A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 0 A9 A8 0 D7 D6 D5 D4 D3 D2 D1 D0
SCL
S
1
2
3
4
5
SSPIF
(PIR1<3>)
Cleared in software
BF (SSPSTAT<0>)
SSPBUF is written with contents of SSPSR
SSPOV (SSPCON<6>)
UA (SSPSTAT<1>)
UA is set indicating that the SSPADD needs to be updated
I2CTM SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
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CKP
(CKP does not reset to `0' when SEN = 0)
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14.13 Master Mode
Master mode of operation is supported in firmware using interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the SSP module is disabled. The Stop (P) and Start (S) bits will toggle based on the Start and Stop conditions. Control of the I2C bus may be taken when the P bit is set or the bus is idle and both the S and P bits are clear. In Master mode, the SCL and SDA lines are manipulated by clearing the corresponding TRISC<7,6> bit(s). The output level is always low, irrespective of the value(s) in PORTC<7,6>. So when transmitting data, a `1' data bit must have the TRISC<6> bit set (input) and a `0' data bit must have the TRISC<7> bit cleared (output). The same scenario is true for the SCL line with the TRISC<6> bit. Pull-up resistors must be provided externally to the SCL and SDA pins for proper operation of the I2C module. The following events will cause the SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt will occur if enabled): * Start condition * Stop condition * Data transfer byte transmitted/received Master mode of operation can be done with either the Slave mode idle (SSPM<3:0> = 1011), or with the Slave active. When both Master and Slave modes are enabled, the software needs to differentiate the source(s) of the interrupt.
14.14 Multi-Master Mode
In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions, allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the SSP module is disabled. The Stop (P) and Start (S) bits will toggle based on the Start and Stop conditions. Control of the I2C bus may be taken when bit P (SSPSTAT<4>) is set, or the bus is idle and both the S and P bits clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt when the Stop condition occurs. In Multi-Master operation, the SDA line must be monitored to see if the signal level is the expected output level. This check only needs to be done when a high level is output. If a high level is expected and a low level is present, the device needs to release the SDA and SCL lines (set TRISC<7,6>). There are two stages where this arbitration can be lost, these are: * Address Transfer * Data Transfer When the slave logic is enabled, the slave continues to receive. If arbitration was lost during the address transfer stage, communication to the device may be in progress. If addressed, an ACK pulse will be generated. If arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time.
14.14.1
CLOCK SYNCHRONIZATION AND THE CKP BIT
When the CKP bit is cleared, the SCL output is forced to `0'; however, setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 14-12).
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FIGURE 14-12: CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX
DX-1
SCL
CKP
Master device asserts clock Master device deasserts clock
WR SSPCON
TABLE 14-4:
Name INTCON LCDCON LCDSE1 PIE1 PIR1 RCSTA SSPBUF SSPCON SSPSTAT TRISC Legend: Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH I2CTM OPERATION
Bit 7 GIE Bit 6 PEIE SLPEN SE14 ADIE ADIF RX9 SSPOV CKE
(1)
Bit 5 T0IE WERR SE13 RCIE RCIF SREN SSPEN D/A TRISC5
Bit 4 INTE VLCDEN SE12 TXIE TXIF CREN CKP P TRISC4
Bit 3 RBIE CS1 SE11 SSPIE SSPIF ADDEN SSPM3 S TRISC3
Bit 2 T0IF CS0 SE10 CCP1IE CCP1IF FERR SSPM2 R/W TRISC2
Bit 1 INTF LMUX1 SE9 TMR2IF TMR2IF OERR SSPM1 UA TRISC1
Bit 0 RBIF LMUX0 SE8 TMR1IF TMR1IF RX9D SSPM0 BF TRISC0
Value on POR, BOR 0000 000x 0001 0011 0000 0000 0000 0000 0000 0000 0000 000x xxxx xxxx 0000 0000 0000 0000 1111 1111
Value on all other Resets 0000 000x 0001 0011 0000 0000 0000 0000 0000 0000 0000 000x uuuu uuuu 0000 0000 0000 0000 1111 1111
LCDEN SE15 EEIE EEIF SPEN WCOL SMP
(1)
Synchronous Serial Port Receive Buffer/Transmit Register
TRISC7
TRISC6
- = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the SSP module. Maintain these bits clear.
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NOTES:
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15.0 CAPTURE/COMPARE/PWM (CCP) MODULE
TABLE 15-1: CCP MODE - TIMER RESOURCES REQUIRED
Timer Resource Timer1 Timer1 Timer2 CCP Mode Capture Compare PWM
The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle. The timer resources used by the module are shown in Table 15-1. Additional information on CCP modules is available in the Application Note AN594, "Using the CCP Modules" (DS00594).
TABLE 15-2:
CCPx Mode Capture Capture Compare PWM PWM PWM
INTERACTION OF TWO CCP MODULES
CCPy Mode Capture Compare Compare PWM Capture Compare Same TMR1 time base Same TMR1 time base Same TMR1 time base The PWMs will have the same frequency and update rate (TMR2 interrupt). The rising edges will be aligned. None None Interaction
Note:
CCPRx and CCPx throughout this document refer to CCPR1 or CCPR2 and CCP1 or CCP2, respectively.
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REGISTER 15-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
CCPxCON: CCPx CONTROL REGISTER
U-0 -- R/W-0 CCPxX R/W-0 CCPxY R/W-0 CCP1M3 R/W-0 CCP1M2 R/W-0 CCP1M1 R/W-0 CCP1M0 bit 0
Unimplemented: Read as `0' CCPxX:CCPxY: PWM Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. CCPxM<3:0>: CCP Mode Select bits 0000 = Capture/Compare/PWM off (resets CCP module) 0001 = Unused (reserved) 0010 = Unused (reserved) 0011 = Unused (reserved) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCPxIF bit is set) 1001 = Compare mode, clear output on match (CCPxIF bit is set) 1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected) 1011 = Compare mode, trigger special event (CCPxIF bit is set, TMR1 is reset and A/D conversion is started if the ADC module is enabled. CCPx pin is unaffected.) 11xx = PWM mode.
bit 3-0
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15.1 Capture Mode
15.1.2 TIMER1 MODE SELECTION
In Capture mode, CCPRxH:CCPRxL captures the 16-bit value of the TMR1 register when an event occurs on pin CCPx. An event is defined as one of the following and is configured by the CCPxM<3:0> bits of the CCPxCON register: * * * * Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work.
15.1.3
SOFTWARE INTERRUPT
When a capture is made, the Interrupt Request Flag bit CCPxIF of the PIRx register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPRxH, CCPRxL register pair is read, the old captured value is overwritten by the new captured value (see Figure 15-1).
When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit of the PIEx register clear to avoid false interrupts. Additionally, the user should clear the CCPxIF interrupt flag bit of the PIRx register following any change in operating mode.
15.1.4
CCP PRESCALER
15.1.1
CCPx PIN CONFIGURATION
In Capture mode, the CCPx pin should be configured as an input by setting the associated TRIS control bit. Note: If the CCPx pin is configured as an output, a write to the port can cause a capture condition.
There are four prescaler settings specified by the CCPxM<3:0> bits of the CCPxCON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCPxCON register before changing the prescaler (see Example 15-1).
FIGURE 15-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Set Flag bit CCPxIF (PIRx register)
EXAMPLE 15-1:
BANKSEL CCP1CON CLRF MOVLW
CHANGING BETWEEN CAPTURE PRESCALERS
Prescaler / 1, 4, 16 CCPx pin
CCPRxH and Edge Detect Capture Enable TMR1H
CCPRxL
MOVWF
TMR1L
;Set Bank bits to point ;to CCP1CON CCP1CON ;Turn CCP module off NEW_CAPT_PS ;Load the W reg with ; the new prescaler ; move value and CCP ON CCP1CON ;Load CCP1CON with this ; value
CCPxCON<3:0> System Clock (FOSC)
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15.2 Compare Mode
15.2.2 TIMER1 MODE SELECTION
In Compare mode, the 16-bit CCPRx register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCPx module may: * * * * * Toggle the CCPx output. Set the CCPx output. Clear the CCPx output. Generate a Special Event Trigger. Generate a Software Interrupt. In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode.
15.2.3
SOFTWARE INTERRUPT MODE
The action on the pin is based on the value of the CCPxM<3:0> control bits of the CCPxCON register. All Compare modes can generate an interrupt.
When Generate Software Interrupt mode is chosen (CCPxM<3:0> = 1010), the CCPx module does not assert control of the CCPx pin (see the CCPxCON register).
15.2.4
SPECIAL EVENT TRIGGER
FIGURE 15-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
CCPxCON<3:0> Mode Select Set CCPxIF Interrupt Flag (PIRx) 4 CCPRxH CCPRxL
When Special Event Trigger mode is chosen (CCPxM<3:0> = 1011), the CCPx module does the following: * Resets Timer1 * Starts an ADC conversion if ADC is enabled The CCPx module does not assert control of the CCPx pin in this mode (see the CCPxCON register). The Special Event Trigger output of the CCP occurs immediately upon a match between the TMR1H, TMR1L register pair and the CCPRxH, CCPRxL register pair. The TMR1H, TMR1L register pair is not reset until the next rising edge of the Timer1 clock. This allows the CCPRxH, CCPRxL register pair to effectively provide a 16-bit programmable period register for Timer1. Note 1: The Special Event Trigger from the CCP module does not set interrupt flag bit TMRxIF of the PIR1 register. 2: Removing the match condition by changing the contents of the CCPRxH and CCPRxL register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring.
CCPx Pin Q S R TRIS Output Enable
Output Logic
Match
Comparator TMR1H TMR1L
Special Event Trigger Special Event Trigger will: * Clear TMR1H and TMR1L registers. * NOT set interrupt flag bit TMR1IF of the PIR1 register. * Set the GO/DONE bit to start the ADC conversion.
15.2.1
CCPx PIN CONFIGURATION
The user must configure the CCPx pin as an output by clearing the associated TRIS bit. Note: Clearing the CCPxCON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch.
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15.3 PWM Mode
The PWM mode generates a Pulse-Width Modulated signal on the CCPx pin. The duty cycle, period and resolution are determined by the following registers: * * * * PR2 T2CON CCPRxL CCPxCON The PWM output (Figure 15-2) has a time base (period) and a time that the output stays high (duty cycle).
FIGURE 15-4:
Period Pulse Width
CCP PWM OUTPUT
TMR2 = PR2 TMR2 = CCPRxL:CCPxCON<5:4>
In Pulse-Width Modulation (PWM) mode, the CCP module produces up to a 10-bit resolution PWM output on the CCPx pin. Since the CCPx pin is multiplexed with the PORT data latch, the TRIS for that pin must be cleared to enable the CCPx pin output driver. Note: Clearing the CCPxCON register will relinquish CCPx control of the CCPx pin.
TMR2 = 0
Figure 15-3 shows a simplified block diagram of PWM operation. Figure 15-4 shows a typical waveform of the PWM signal. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 15.3.7 "Setup for PWM Operation".
FIGURE 15-3:
SIMPLIFIED PWM BLOCK DIAGRAM
CCPxCON<5:4>
Duty Cycle Registers CCPRxL
CCPRxH(2) (Slave) CCPx Comparator
(1)
R S
Q
TMR2
TRIS Comparator
PR2
Clear Timer2, toggle CCPx pin and latch duty cycle
Note 1:
2:
The 8-bit timer TMR2 register is concatenated with the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. In PWM mode, CCPRxH is a read-only register.
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15.3.1 PWM PERIOD EQUATION 15-2: PULSE WIDTH
The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 15-1. Pulse Width = ( CCPRxL:CCPxCON<5:4> ) * TOSC * (TMR2 Prescale Value)
EQUATION 15-1:
PWM PERIOD EQUATION 15-3: DUTY CYCLE RATIO
PWM Period = [ ( PR2 ) + 1 ] * 4 * TOSC * (TMR2 Prescale Value) Note: TOSC = 1/FOSC
( CCPRxL:CCPxCON<5:4> ) Duty Cycle Ratio = ---------------------------------------------------------------------4 ( PR2 + 1 ) The CCPRxH register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. When the 10-bit time base matches the CCPRxH and 2-bit latch, then the CCPx pin is cleared (see Figure 15-3).
When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) * The PWM duty cycle is latched from CCPRxL into CCPRxH. Note: The Timer2 postscaler (see Section 7.1 "Timer2 Operation") is not used in the determination of the PWM frequency.
15.3.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPRxL register and CCPx<1:0> bits of the CCPxCON register. The CCPRxL contains the eight MSbs and the CCPx<1:0> bits of the CCPxCON register contain the two LSbs. CCPRxL and CCPx<1:0> bits of the CCPxCON register can be written to at any time. The duty cycle value is not latched into CCPRxH until after the period completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPRxH register is read-only. Equation 15-2 is used to calculate the PWM pulse width. Equation 15-3 is used to calculate the PWM duty cycle ratio.
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15.3.3 PWM RESOLUTION EQUATION 15-4: PWM RESOLUTION
The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 15-4. Note: log [ 4 ( PR2 + 1 ) ] Resolution = ----------------------------------------- bits log ( 2 )
If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged.
TABLE 15-3:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
1.22 kHz 16 0xFF 10 4.88 kHz 4 0xFF 10 19.53 kHz 1 0xFF 10 78.12 kHz 1 0x3F 8 156.3 kHz 1 0x1F 7 208.3 kHz 1 0x17 6.6
PWM Frequency Timer Prescale (1, 4, 16) PR2 Value Maximum Resolution (bits)
TABLE 15-4:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
1.22 kHz 16 0x65 8 4.90 kHz 4 0x65 8 19.61 kHz 1 0x65 8 76.92 kHz 1 0x19 6 153.85 kHz 1 0x0C 5 200.0 kHz 1 0x09 5
PWM Frequency Timer Prescale (1, 4, 16) PR2 Value Maximum Resolution (bits)
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15.3.4 OPERATION IN SLEEP MODE 15.3.7 SETUP FOR PWM OPERATION
In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. Disable the PWM pin (CCPx) output drivers by setting the associated TRIS bit. Set the PWM period by loading the PR2 register. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. Set the PWM duty cycle by loading the CCPRxL register and CCPx bits of the CCPxCON register. Configure and start Timer2: * Clear the TMR2IF interrupt flag bit of the PIR1 register. * Set the Timer2 prescale value by loading the T2CKPS bits of the T2CON register. * Enable Timer2 by setting the TMR2ON bit of the T2CON register. Enable PWM output after a new PWM cycle has started: * Wait until Timer2 overflows (TMR2IF bit of the PIR1 register is set). * Enable the CCPx pin output driver by clearing the associated TRIS bit.
15.3.5
CHANGES IN SYSTEM CLOCK FREQUENCY
The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 4.0 "Oscillator Module (With Fail-Safe Clock Monitor)" for additional details.
4. 5.
15.3.6
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the CCP registers to their Reset states. 6.
TABLE 15-5:
Name CCPxCON CCPRxL CCPRxH CMCON1 INTCON LCDCON LCDSE1 PIE1 PIE2 PIR1 PIR2 RCSTA SSPCON T1CON T2CON TMR1L TMR1H TMR2 TRISC TRISD
(1)
SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND PWM
Bit 6 -- Bit 5 CCPxX Bit 4 CCPxY Bit 3 CCPxM3 Bit 2 CCPxM2 Bit 1 CCPxM1 Bit 0 CCPxM0 Value on POR, BOR Value on all other Resets
Bit 7 --
--00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register X Low Byte Capture/Compare/PWM Register X High Byte -- GIE LCDEN SE15 EEIE OSFIE EEIF OSFIF SPEN WCOL T1GINV -- -- PEIE SLPEN SE14 ADIE C2IE ADIF C2IF RX9 SSPOV -- T0IE WERR SE13 RCIE C1IE RCIF C1IF SREN SSPEN -- INTE VLCDEN SE12 TXIE LCDIE TXIF LCDIF CREN CKP -- RBIE CS1 SE11 SSPIE -- SSPIF -- ADDEN SSPM3 -- T0IF CS0 SE10 CCP1IE LVDIE CCP1IF LVDIF FERR SSPM2 T1GSS INTF LMUX1 SE9 TMR2IE -- TMR2IF -- OERR SSPM1 TMR1CS RBIF LMUX0 SE8 TMR1IE CCP2IE TMR1IF CCP2IF RX9D SSPM0
C2SYNC ---- --10 ---- --10 0000 000x 0000 000x 0001 0011 0001 0011 0000 0000 0000 0000 0000 0000 0000 0000 0000 -0-0 0000 -0-0 0000 0000 0000 0000 0000 -0-0 0000 -0-0 0000 000x 0000 000x 0000 0000 0000 0000
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1ON 0000 0000 uuuu uuuu
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 0000 0000 0000 0000 TRISC5 TRISD5 TRISC4 TRISD4 TRISC3 TRISD3 TRISC2 TRISD2 TRISC1 TRISD1 TRISC0 TRISD0 1111 1111 1111 1111 1111 1111 1111 1111
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register Timer2 Module Register TRISC7 TRISD7 TRISC6 TRISD6
Legend: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the Capture, Compare and PWM. Note 1: PIC16F914/917 and PIC16F946 only.
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16.0 SPECIAL FEATURES OF THE CPU
The PIC16F91X/946 has two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 64 ms (nominal) on power-up only, designed to keep the part in Reset while the power supply stabilizes. There is also circuitry to reset the device if a brown-out occurs, which can use the Power-up Timer to provide at least a 64 ms Reset. With these three functions-on-chip, most applications need no external Reset circuitry. The Sleep mode is designed to offer a very low-current Power-down mode. The user can wake-up from Sleep through: * External Reset * Watchdog Timer Wake-up * An interrupt Several oscillator options are also made available to allow the part to fit the application. The INTOSC option saves system cost, while the LP crystal option saves power. A set of Configuration bits are used to select various options (see Register 16-1).
The PIC16F91X/946 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power-saving features and offer code protection. These features are: * Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * Oscillator Selection * Sleep * Code Protection * ID Locations * In-Circuit Serial ProgrammingTM
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16.1 Configuration Bits
The Configuration bits can be programmed (read as `0'), or left unprogrammed (read as `1') to select various device configurations as shown in Register 16-1. These bits are mapped in program memory location 2007h. Note: Address 2007h is beyond the user program memory space. It belongs to the special configuration memory space (2000h-3FFFh), which can be accessed only during programming. See "PIC16F91X/946 Memory Programming Specification" (DS41244) for more information.
REGISTER 16-1:
-- bit 15
CONFIG1: CONFIGURATION WORD REGISTER 1
-- -- DEBUG FCMEN IESO BOREN1 BOREN0 bit 8
CPD bit 7 bit 15-13 bit 12
CP
MCLRE
PWRTE
WDTE
FOSC2
FOSC1
FOSC0 bit 0
Unimplemented: Read as `1' DEBUG: In-Circuit Debugger Mode bit 1 = In-Circuit Debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger FCMEN: Fail-Safe Clock Monitor Enabled bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled IESO: Internal External Switchover bit 1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled BOREN<1:0>: Brown-out Reset Selection bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the PCON register 00 = BOR disabled CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled CP: Code Protection bit(3) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled MCLRE: RE3/MCLR pin function select bit(4) 1 = RE3/MCLR pin function is MCLR 0 = RE3/MCLR pin function is digital input, MCLR internally tied to VDD PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled and can be enabled by SWDTEN bit of the WDTCON register FOSC<2:0>: Oscillator Selection bits 111 = RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT/T1OSO pin, RC on RA7/OSC1/CLKIN/T1OSI 110 = RCIO oscillator: I/O function on RA6/OSC2/CLKOUT/T1OSO pin, RC on RA7/OSC1/CLKIN/T1OSI 101 = INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT/T1OSO pin, I/O function on RA7/OSC1/CLKIN/T1OSI 100 = INTOSCIO oscillator: I/O function on RA6/OSC2/CLKOUT/T1OSO pin, I/O function on RA7/OSC1/CLKIN/T1OSI 011 = EC: I/O function on RA6/OSC2/CLKOUT/T1OSO pin, CLKIN on RA7/OSC1/CLKIN/T1OSI 010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT/T1OSO and RA7/OSC1/CLKIN/T1OSI 001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT/T1OSO and RA7/OSC1/CLKIN/T1OSI 000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT/T1OSO and RA7/OSC1/CLKIN/T1OSI
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note
1: 2: 3: 4:
Enabling Brown-out Reset does not automatically enable Power-up Timer. The entire data EEPROM will be erased when the code protection is turned off. The entire program memory will be erased when the code protection is turned off. When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
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16.2 Resets
The PIC16F91X/946 differentiates between various kinds of Reset: a) b) c) d) e) f) Power-on Reset (POR) WDT Reset during normal operation WDT Reset during Sleep MCLR Reset during normal operation MCLR Reset during Sleep Brown-out Reset (BOR) They are not affected by a WDT wake-up since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 16-2. These bits are used in software to determine the nature of the Reset. See Table 16-5 for a full description of Reset states of all registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 16-1. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section 19.0 "Electrical Specifications" for pulse width specifications.
Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a "Reset state" on: * * * * * Power-on Reset MCLR Reset MCLR Reset during Sleep WDT Reset Brown-out Reset (BOR)
FIGURE 16-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR/VPP pin WDT Module VDD Rise Detect VDD
Sleep WDT Time-out Reset
Power-on Reset Brown-out(1) Reset BOREN SBOREN
S
OST/PWRT OST 10-bit Ripple Counter OSC1/ CLKIN pin PWRT LFINTOSC 11-bit Ripple Counter R Q Chip_Reset
Enable PWRT Enable OST
Note
1:
Refer to the Configuration Word register (Register 16-1).
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16.2.1 POWER-ON RESET (POR) FIGURE 16-2:
VDD R1 1 k (or greater) MCLR C1 0.1 F (optional, not critical)
The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply connect the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Section 19.0 "Electrical Specifications" for details. If the BOR is enabled, the maximum rise time specification does not apply. The BOR circuitry will keep the device in Reset until VDD reaches VBOR (see Section 16.2.4 "Brown-Out Reset (BOR)"). Note: The POR circuit does not produce an internal Reset when VDD declines. To re-enable the POR, VDD must reach Vss for a minimum of 100 s.
RECOMMENDED MCLR CIRCUIT
PIC(R) MCU
16.2.3
POWER-UP TIMER (PWRT)
When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting" (DS00607).
16.2.2
MCLR
The Power-up Timer provides a fixed 64 ms (nominal) time-out on power-up only, from POR or Brown-out Reset. The Power-up Timer operates from the 31 kHz LFINTOSC oscillator. For more information, see Section 4.5 "Internal Clock Modes". The chip is kept in Reset as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A Configuration bit, PWRTE, can disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-up Timer should be enabled when Brown-out Reset is enabled, although it is not required. The Power-up Timer delay will vary from chip-to-chip and vary due to: * VDD variation * Temperature variation * Process variation See DC parameters for details "Electrical Specifications"). (Section 19.0
PIC16F91X/946 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure 16-2, is suggested. An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word register. When MCLRE = 0, the Reset signal to the chip is generated internally. When the MCLRE = 1, the RE3/MCLR pin becomes an external Reset input. In this mode, the RE3/MCLR pin has a weak pull-up to VDD. In-Circuit Serial Programming is not affected by selecting the internal MCLR option.
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16.2.4 BROWN-OUT RESET (BOR)
The BOREN0 and BOREN1 bits in the Configuration Word register selects one of four BOR modes. Two modes have been added to allow software or hardware control of the BOR enable. When BOREN<1:0> = 01, the SBOREN bit of the PCON register enables/disables the BOR allowing it to be controlled in software. By selecting BOREN<1:0>, the BOR is automatically disabled in Sleep to conserve power and enabled on wake-up. In this mode, the SBOREN bit is disabled. See Register 16-1 for the Configuration Word definition. If VDD falls below VBOR for greater than parameter (TBOR) (see Section 19.0 "Electrical Specifications"), the Brown-out situation will reset the device. This will occur regardless of VDD slew rate. A Reset is not insured to occur if VDD falls below VBOR for less than parameter (TBOR). On any Reset (Power-on, Brown-out Reset, Watchdog Timer, etc.), the chip will remain in Reset until VDD rises above VBOR (see Figure 16-3). The Power-up Timer will now be invoked, if enabled and will keep the chip in Reset an additional 64 ms. Note: The Power-up Timer is enabled by the PWRTE bit in the Configuration Word. If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. Once VDD rises above VBOR, the Power-up Timer will execute a 64 ms Reset.
16.2.5
BOR CALIBRATION
The PIC16F91X/946 stores the BOR calibration values in fuses located in the Calibration Word (2008h). The Calibration Word is not erased when using the specified bulk erase sequence in the "PIC16F91X/946 Memory Programming Specification" (DS41244) and thus, does not require reprogramming. Address 2008h is beyond the user program memory space. It belongs to the special configuration memory space (2000h-3FFFh), which can be accessed only during programming. See "PIC16F91X/946 Memory Programming Specification" (DS41244) for more information.
FIGURE 16-3:
VDD
BROWN-OUT SITUATIONS
VBOR
Internal Reset VDD
64 ms(1)
VBOR < 64 ms
Internal Reset
64 ms(1)
VDD
VBOR
Internal Reset Note 1: 64 ms delay only if PWRTE bit is programmed to `0'.
64 ms(1)
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16.2.6 TIME-OUT SEQUENCE 16.2.7
On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after POR has expired, then OST is activated after the PWRT time-out has expired. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 16-4, Figure 16-5 and Figure 16-6 depict time-out sequences. The device can execute code from the INTOSC while OST is active, by enabling Two-Speed Start-up or Fail-Safe Monitor (see Section 4.7.2 "Two-Speed Start-up Sequence" and Section 4.8 "Fail-Safe Clock Monitor"). Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then, bringing MCLR high will begin execution immediately (see Figure 16-5). This is useful for testing purposes or to synchronize more than one PIC16F91X/946 device operating in parallel. Table 16-5 shows the Reset conditions for some special registers, while Table 16-5 shows the Reset conditions for all the registers.
POWER CONTROL (PCON) REGISTER
The Power Control (PCON) register (address 8Eh) has two Status bits to indicate what type of Reset that last occurred. Bit 0 is BOR (Brown-out Reset). BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent Resets to see if BOR = 0, indicating that a Brown-out has occurred. The BOR Status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (BOREN<1:0> = 00 in the Configuration Word register). Bit 1 is POR (Power-on Reset). It is a `0' on Power-on Reset and unaffected otherwise. The user must write a `1' to this bit following a Power-on Reset. On a subsequent Reset, if POR is `0', it will indicate that a Power-on Reset has occurred (i.e., VDD may have gone too low). For more information, see Section 16.2.4 "Brown-Out Reset (BOR)".
TABLE 16-1:
TIME-OUT IN VARIOUS SITUATIONS
Power-up PWRTE = 0 TPWRT + 1024 * TOSC TPWRT PWRTE = 1 1024 * TOSC -- Brown-out Reset PWRTE = 0 TPWRT + 1024 * TOSC TPWRT PWRTE = 1 1024 * TOSC -- Wake-up from Sleep 1024 * TOSC --
Oscillator Configuration XT, HS, LP(1) RC, EC, INTOSC Note 1:
LP mode with T1OSC disabled.
TABLE 16-2:
POR 0 1 u u u u u 0 u u u u
PCON BITS AND THEIR SIGNIFICANCE
TO 1 1 0 0 u 1 PD 1 1 u 0 u 0 Power-on Reset Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during Sleep Condition
BOR
Legend: u = unchanged, x = unknown
TABLE 16-3:
Name STATUS PCON
Legend: Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
Bit 7 IRP -- Bit 6 RP1 -- Bit 5 RP0 -- Bit 4 TO SBOREN Bit 3 PD -- Bit 2 Z -- Bit 1 DC POR Bit 0 C BOR Value on POR, BOR 0001 1xxx --01 --qq Value on all other Resets(1) 000q quuu --0u --uu
u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. Shaded cells are not used by BOR. Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
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FIGURE 16-4:
VDD MCLR Internal POR TPWRT PWRT Time-out OST Time-out Internal Reset TOST
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1
FIGURE 16-5:
VDD MCLR Internal POR
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2
TPWRT PWRT Time-out OST Time-out Internal Reset TOST
FIGURE 16-6:
VDD MCLR Internal POR
TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD): CASE 3
TPWRT PWRT Time-out OST Time-out Internal Reset TOST
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TABLE 16-4:
Register W INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(6) PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG
INITIALIZATION CONDITION FOR REGISTERS
Address -- 00h/80h/ 100h/180h 01h/101h 02h/82h/ 102h/182h 03h/83h/ 103h/183h 04h/84h/ 104h/184h 05h 06h/106h 07h 08h 09h 0Ah/8Ah/ 10Ah/18Ah 0Bh/8Bh/ 10Bh/18Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h Power-on Reset * MCLR Reset * WDT Reset * Brown-out Reset(1) uuuu uuuu xxxx xxxx uuuu uuuu 0000 0000 000q quuu(4) uuuu uuuu xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ---- xxxx xxxx xxxx(7) ---0 0000 0000 000x 0000 0000 0000 -0-0 uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 -000 0000 xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx --00 0000 ---0 1000 0000 0000 * Wake-up from Sleep through interrupt * Wake-up from Sleep through WDT time-out uuuu uuuu uuuu uuuu uuuu uuuu PC + 1(3) uuuq quuu(4) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- uuuu uuuu uuuu(7) ---u uuuu uuuu uuuu(2) uuuu uuuu(2) uuuu -u-u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu ---u uuuu uuuu uuuu
xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ---- xxxx xxxx xxxx(7) ---0 0000 0000 000x 0000 0000 0000 -0-0 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 -000 0000 xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx --00 0000 ---0 1000 0000 0000
-
Legend: u = unchanged, x = unknown, = unimplemented bit, reads as `0', q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 4: See Table 16-5 for Reset value for specific condition. 5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. 6: PIC16F914/917 and PIC16F946 only. 7: PIC16F946 only.
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TABLE 16-4:
Register RCREG CCPR2L(6) CCPR2H(6) CCP2CON(6) ADRESH ADCON0 OPTION_REG TRISA TRISB TRISC TRISD TRISE PIE1 PIE2 PCON OSCCON OSCTUNE ANSEL PR2 SSPADD SSPSTAT WPUB IOCB CMCON1 TXSTA SPBRG CMCON0 VRCON ADRESL ADCON1 WDTCON LCDCON LCDPS Legend: Note 1: 2: 3: 4: 5: 6: 7:
(6)
INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
Address 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 81h/181h 85h 86h/186h 87h 88h 89h 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ch 9Dh 9Eh 9Fh 105h 107h 108h Power-on Reset * MCLR Reset * WDT Reset * Brown-out Reset(1) 0000 0000 xxxx xxxx xxxx xxxx --00 0000 uuuu uuuu 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 1111 1111(7) 0000 0000 0000 -0-0 --0u --uu
(1,5)
* Wake-up from Sleep through interrupt * Wake-up from Sleep through WDT time-out uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- uuuu uuuu uuuu(7) uuuu uuuu uuuu -u-u --uu --uu -uuu uuuu ---u uuuu uuuu uuuu 1111 1111 uuuu uuuu uuuu uuuu uuuu uuuu uuuu ------- --uu uuuu -uuu uuuu uuuu uuuu uuuu u-u- uuuu uuuu uuuu -uuu ------u uuuu uuuu uuuu uuuu uuuu
0000 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 1111 1111(7) 0000 0000 0000 -0-0 --01 --0x -110 q000 ---0 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 0000 ------- --10 0000 -010 0000 0000 0000 0000 0-0- 0000 xxxx xxxx -000 ------0 1000 0001 0011 0000 0000
-110 x000 ---u uuuu 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 0000 ------- --10 0000 -010 0000 0000 0000 0000 0-0- 0000 uuuu uuuu -000 ------0 1000 0001 0011 0000 0000
u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 16-5 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. PIC16F914/917 and PIC16F946 only. PIC16F946 only.
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TABLE 16-4:
Register LVDCON EEDATL EEADRL EEDATH EEADRH LCDDATA0 LCDDATA1 LCDDATA2(6) LCDDATA3 LCDDATA4 LCDDATA5 LCDDATA6 LCDDATA7 LCDDATA8(6) LCDDATA9 LCDDATA10 LCDDATA11 LCDSE0 LCDSE1 LCDSE2(6) TRISF(7) TRISG(7) PORTF(7) PORTG(7) LCDDATA12(7) LCDDATA13(7) LCDDATA14(7) LCDDATA15(7) LCDDATA16(7) LCDDATA17(7) LCDDATA18(7) LCDDATA19(7) LCDDATA20(7) LCDDATA21(7) Legend: Note 1: 2: 3: 4: 5: 6: 7:
(6) (6)
INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
Address 109h 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 185h 187h 188h 189h 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h Power-on Reset * MCLR Reset * WDT Reset * Brown-out Reset(1) --00 -100 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 1111 1111 --11 1111 0000 0000 --00 0000 uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu * Wake-up from Sleep through interrupt * Wake-up from Sleep through WDT time-out --uu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu
--00 -100 0000 0000 0000 0000 --00 0000 ---0 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 1111 1111 --11 1111 xxxx xxxx --xx xxxx xxxx xxxx xxxx xxxx ---- --xx xxxx xxxx xxxx xxxx ---- --xx xxxx xxxx xxxx xxxx ---- --xx xxxx xxxx
u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 16-5 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. PIC16F914/917 and PIC16F946 only. PIC16F946 only.
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TABLE 16-4:
Register LCDDATA22(7) LCDDATA23(7) LCDSE3(7) LCDSE4(7) LCDSE5 Legend: Note 1: 2: 3: 4: 5: 6: 7:
(7)
INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
Address 19Ah 19Bh 19Ch 19Dh 19Eh 18Ch Power-on Reset * MCLR Reset * WDT Reset * Brown-out Reset(1) uuuu uuuu ---- --uu uuuu uuuu uuuu uuuu ---- --uu u--- q000 * Wake-up from Sleep through interrupt * Wake-up from Sleep through WDT time-out uuuu uuuu ---- --uu uuuu uuuu uuuu uuuu ---- --uu u--- uuuu
xxxx xxxx ---- --xx 0000 0000 0000 0000 ---- --00 x--- x000
EECON1
u = unchanged, x = unknown, - = unimplemented bit, reads as `0', q = value depends on condition. If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 16-5 for Reset value for specific condition. If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. PIC16F914/917 and PIC16F946 only. PIC16F946 only.
TABLE 16-5:
INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Condition Program Counter 0000h 0000h 0000h 0000h PC + 1 0000h PC + 1
(1)
STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 uuuu uuu0 0uuu 0001 1uuu uuu1 0uuu
PCON Register ---1 --0x ---u --uu ---u --uu ---u --uu ---u --uu ---1 --10 ---u --uu
Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset WDT Wake-up Brown-out Reset Interrupt Wake-up from Sleep
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
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16.3
* * * * * * * * * * * * *
Interrupts
The PIC16F91X/946 has multiple sources of interrupt: External Interrupt RB0/INT/SEG0 TMR0 Overflow Interrupt PORTB Change Interrupts 2 Comparator Interrupts A/D Interrupt Timer1 Overflow Interrupt EEPROM Data Write Interrupt Fail-Safe Clock Monitor Interrupt LCD Interrupt PLVD Interrupt USART Receive and Transmit interrupts CCP1 and CCP2 Interrupts Timer2 Interrupt
The following interrupt flags are contained in the PIR2 register: * * * * * Fail-Safe Clock Monitor Interrupt Comparator 1 and 2 Interrupts LCD Interrupt PLVD Interrupt CCP2 Interrupt
When an interrupt is serviced: * The GIE is cleared to disable any further interrupt. * The return address is pushed onto the stack. * The PC is loaded with 0004h. For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event occurs (see Figure 16-8). The latency is the same for one or two-cycle instructions. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. Note 1: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. 2: When an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The interrupts, which were ignored, are still pending to be serviced when the GIE bit is set again. For additional information on how a module generates an interrupt, refer to the respective peripheral section. Note: The ANSEL and CMCON0 registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'. Also, if a LCD output function is active on an external interrupt pin, that interrupt function will be disabled.
The Interrupt Control (INTCON), Peripheral Interrupt Request 1 (PIR1) and Peripheral Interrupt Request 2 (PIR2) registers record individual interrupt requests in flag bits. The INTCON register also has individual and global interrupt enable bits. A Global Interrupt Enable bit, GIE of the INTCON register, enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in the INTCON, PIE1 and PIE2 registers. GIE is cleared on Reset. The Return from Interrupt instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables unmasked interrupts. The following interrupt flags are contained in the INTCON register: * INT Pin Interrupt * PORTB Change Interrupt * TMR0 Overflow Interrupt The peripheral interrupt flags are contained in the special registers, PIR1 and PIR2. The corresponding interrupt enable bit are contained in the special registers, PIE1 and PIE2. The following interrupt flags are contained in the PIR1 register: * * * * * * * EEPROM Data Write Interrupt A/D Interrupt USART Receive and Transmit Interrupts Timer1 Overflow Interrupt CCP1 Interrupt SSP Interrupt Timer2 Interrupt
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16.3.1 RB0/INT/SEG0 INTERRUPT 16.3.2 TMR0 INTERRUPT
External interrupt on RB0/INT/SEG0 pin is edge-triggered; either rising if the INTEDG bit of the OPTION register is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT/SEG0 pin, the INTF bit of the INTCON register is set. This interrupt can be disabled by clearing the INTE control bit of the INTCON register. The INTF bit must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt. The RB0/INT/SEG0 interrupt can wake-up the processor from Sleep if the INTE bit was set prior to going into Sleep. The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wake-up (0004h). See Section 16.5 "Power-Down Mode (Sleep)" for details on Sleep and Figure 16-10 for timing of wake-up from Sleep through RB0/INT/SEG0 interrupt. An overflow (FFh 00h) in the TMR0 register will set the T0IF bit of the INTCON register. The interrupt can be enabled/disabled by setting/clearing T0IE bit of the INTCON register. See Section 5.0 "Timer0 Module" for operation of the Timer0 module.
16.3.3
PORTB INTERRUPT
An input change on PORTB change sets the RBIF bit of the INTCON register. The interrupt can be enabled/disabled by setting/clearing the RBIE bit of the INTCON register. Plus, individual pins can be configured through the IOCB register. Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not get set.
FIGURE 16-7:
IOC-RB4 IOCB4 IOC-RB5 IOCB5 IOC-RB6 IOCB6 IOC-RB7 IOCB7 TMR2IF TMR2IE TMR1IF TMR1IE C1IF C1IE C2IF C2IE ADIF ADIE OSFIF OSFIE EEIF EEIE CCP1IF CCP1IE CCP2IF CCP2IE RCIF RCIE TXIF TXIE SSPIF SSPIE LCDIF LCDIE LVDIF LVDIE
INTERRUPT LOGIC
TMR0IF TMR0IE INTF INTE RBIF RBIE PEIF PEIE GIE
Wake-up (If in Sleep mode) Interrupt to CPU
*
* Only available on the PIC16F914/917.
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FIGURE 16-8:
Q1 OSC1 CLKOUT(3) INT pin INTF Flag (INTCON reg.) GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: 5:
(1) (5)
INT PIN INTERRUPT TIMING
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(4) (1)
Interrupt Latency (2)
PC Inst (PC) Inst (PC - 1)
PC + 1 Inst (PC + 1) Inst (PC)
PC + 1 -- Dummy Cycle
0004h Inst (0004h) Dummy Cycle
0005h Inst (0005h) Inst (0004h)
INTF flag is sampled here (every Q1). Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. CLKOUT is available only in INTOSC and RC Oscillator modes. For minimum width of INT pulse, refer to AC specifications in Section 19.0 "Electrical Specifications". INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 16-6:
Name INTCON PIR1 PIR2 PIE1 PIE2 Legend: Bit 7 GIE EEIF
SUMMARY OF INTERRUPT REGISTERS
Bit 6 PEIE ADIF C2IF ADIE C2IE Bit 5 T0IE RCIF C1IF RCIE C1IE Bit 4 INTE TXIF LCDIF TXIE LCDIE Bit 3 RBIE SSPIF -- SSPIE -- Bit 2 T0IF CCP1IF LVDIF CCP1IE LVDIE Bit 1 INTF TMR2IF -- TMR2IE -- Bit 0 RBIF TMR1IF CCP2IF TMR1IE CCP2IE Value on POR, BOR 0000 000x 0000 0000 0000 -0-0 0000 0000 0000 -0-0 Value on all other Resets 0000 000x 0000 0000 0000 -0-0 0000 0000 0000 -0-0
OSFIF EEIE OSFIE
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by the Interrupt Module.
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16.3.4 CONTEXT SAVING DURING INTERRUPTS
During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and STATUS registers). This must be implemented in software. Since the lower 16 bytes of all banks are common in the PIC16F91X/946 (see Figure 2-3), temporary holding registers, W_TEMP and STATUS_TEMP, should be placed in here. These 16 locations do not require banking and therefore, make it easier to context save and restore. The same code shown in Example 16-1 can be used to: * * * * * Store the W register Store the STATUS register Execute the ISR code Restore the STATUS register (Bank Select bits) Restore the W register Note: The microcontroller does not normally require saving the PCLATH register unless it is modified in code either directly or via the pagesel macro. Then, the PCLATH register must be saved at the beginning of the ISR, managed for CALLs and GOTOs in the ISR and restored when the ISR is complete to ensure correct program flow.
EXAMPLE 16-1:
MOVWF SWAPF CLRF MOVWF : :(ISR) : SWAPF MOVWF SWAPF SWAPF
SAVING STATUS AND W REGISTERS IN RAM
;Copy ;Swap ;bank ;Save W to TEMP register status to be saved into W 0, regardless of current bank, Clears IRP,RP1,RP0 status to bank zero STATUS_TEMP register
W_TEMP STATUS,W STATUS STATUS_TEMP
;Insert user code here STATUS_TEMP,W STATUS W_TEMP,F W_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W
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16.4 Watchdog Timer (WDT)
For PIC16F91X/946, the WDT has been modified from previous PIC16F devices. The new WDT is code and functionally compatible with previous PIC16F WDT modules and adds a 16-bit prescaler to the WDT. This allows the user to have a scaled value for the WDT and TMR0 at the same time. In addition, the WDT time-out value can be extended to 268 seconds. WDT is cleared under certain conditions described in Table 16-7. A new prescaler has been added to the path between the INTOSC and the multiplexers used to select the path for the WDT. This prescaler is 16 bits and can be programmed to divide the INTOSC by 32 to 65536, giving the WDT a nominal range of 1 ms to 268s.
16.4.2
WDT CONTROL
The WDTE bit is located in the Configuration Word register. When set, the WDT runs continuously. When the WDTE bit in the Configuration Word register is set, the SWDTEN bit of the WDTCON register has no effect. If WDTE is clear, then the SWDTEN bit can be used to enable and disable the WDT. Setting the bit will enable it and clearing the bit will disable it. The PSA and PS<2:0> bits of the OPTION register have the same function as in previous versions of the PIC16F family of microcontrollers. See Section 5.0 "Timer0 Module" for more information.
16.4.1
WDT OSCILLATOR
The WDT derives its time base from the 31 kHz LFINTOSC. The LTS bit does not reflect that the LFINTOSC is enabled. The value of WDTCON is `---0 1000' on all Resets. This gives a nominal time base of 16 ms, which is compatible with the time base generated with previous PIC16F microcontroller versions. Note: When the Oscillator Start-up Timer (OST) is invoked, the WDT is held in Reset, because the WDT Ripple Counter is used by the OST to perform the oscillator delay count. When the OST count has expired, the WDT will begin counting (if enabled).
FIGURE 16-9:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source 0 Prescaler(1) 16-bit WDT Prescaler 1 8 PSA
PS<2:0> To TMR0 0 1 PSA
31 kHz LFINTOSC Clock
WDTPS<3:0>
WDTE from Configuration Word register SWDTEN from WDTCON WDT Time-out
Note 1: This is the shared Timer0/WDT prescaler. See Section 5.4 "Prescaler" for more information.
TABLE 16-7:
WDTE = 0
WDT STATUS
Conditions WDT
CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP
Cleared
Cleared until the end of OST
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REGISTER 16-2: WDTCON - WATCHDOG TIMER CONTROL REGISTER (ADDRESS: 105h)
U-0 -- bit 7 bit 7-5 bit 4-1 Unimplemented: Read as `0' WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 (Reset value) 0101 = 1:1024 0110 = 1:2048 0111 = 1:4096 1000 = 1:8192 1001 = 1:16384 1010 = 1:32768 1011 = 1:65536 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved SWDTEN: Software Enable or Disable the Watchdog Timer bit(1) 1 = WDT is turned on 0 = WDT is turned off (Reset value) Note 1: If WDTE Configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTE Configuration bit = 0, then it is possible to turn WDT on/off with this control bit. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 WDTPS3 R/W-1 WDTPS2 R/W-0 WDTPS1 R/W-0 WDTPS0 R/W-0 SWDTEN bit 0
bit 0
TABLE 16-8:
Name CONFIG OPTION_REG WDTCON
SUMMARY OF WATCHDOG TIMER REGISTERS
Bit 7 CPD RBPU -- Bit 6 CP INTEDG -- Bit 5 MCLRE T0CS -- Bit 4 PWRTE T0SE WDTPS3 Bit 3 WDTE PSA WDTPS2 Bit 2 FOSC2 PS2 WSTPS1 Bit 1 FOSC1 PS1 WDTPS0 Bit 0 FOSC0 PS0 SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 16-1 for operation of all Configuration Word register bits.
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16.5 Power-Down Mode (Sleep)
The Power-down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: * * * * * * WDT will be cleared but keeps running. PD bit in the STATUS register is cleared. TO bit is set. Oscillator driver is turned off. Timer1 oscillator is unaffected I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance). The following peripheral interrupts can wake the device from Sleep: 1. 2. 3. 4. 5. 6. 7. 8. 9. TMR1 Interrupt. Timer1 must be operating as an asynchronous counter. USART Receive Interrupt (Sync Slave mode only) A/D conversion (when A/D clock source is RC) EEPROM write operation completion Comparator output changes state Interrupt-on-change External Interrupt from INT pin PLVD Interrupt LCD Interrupt (if running during Sleep)
For lowest current consumption in this mode, all I/O pins should be either at VDD or VSS, with no external circuitry drawing current from the I/O pin, and the comparators and CVREF should be disabled. I/O pins that are high-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level. Note: It should be noted that a Reset generated by a WDT time-out does not drive MCLR pin low.
Other peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction, then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. Note: If the global interrupts are disabled (GIE is cleared), but any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set, the device will immediately wake-up from Sleep. The SLEEP instruction is completely executed.
16.5.1
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the following events: 1. 2. 3. External Reset input on MCLR pin. Watchdog Timer wake-up (if WDT was enabled). Interrupt from RB0/INT/SEG0 pin, PORTB change or a peripheral interrupt.
The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up.
The first event will cause a device Reset. The two latter events are considered a continuation of program execution. The TO and PD bits in the STATUS register can be used to determine the cause of device Reset. The PD bit, which is set on power-up, is cleared when Sleep is invoked. TO bit is cleared if WDT wake-up occurred.
16.5.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from Sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will be cleared, the TO bit will be set and the PD bit will be cleared.
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Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
FIGURE 16-10:
OSC1(1) CLKOUT(4) INT pin INTF flag (INTCON reg.) GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TOST(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Interrupt Latency (3) Processor in Sleep
PC Inst(PC) = Sleep Inst(PC - 1)
PC + 1 Inst(PC + 1) Sleep
PC + 2
PC + 2 Inst(PC + 2) Inst(PC + 1)
PC + 2
0004h Inst(0004h)
0005h Inst(0005h) Inst(0004h)
Dummy Cycle
Dummy Cycle
XT, HS or LP Oscillator mode assumed. TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes. GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line. CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
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16.6 Code Protection
FIGURE 16-11:
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out using ICSP for verification purposes. Note: The entire data EEPROM and Flash program memory will be erased when the code protection is turned off. See the "PIC16F91X/946 Memory Programming Specification" (DS41244) for more information.
External Connector Signals +5V 0V VPP
TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
To Normal Connections
*
PIC(R) MCU VDD VSS RE3/MCLR/VPP RB6/ICSPCLK/ ICDCK/SEG14 RB7/ICSPDATA/ ICDDAT/SEG13
16.7
ID Locations
CLK Data I/O
Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used.
*
*
*
16.8
In-Circuit Serial Programming
To Normal Connections * Isolation devices (as required)
The PIC16F91X/946 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for: * power * ground * programming voltage This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a Program/Verify mode by holding the RB7/ICSPDAT/ICDDAT/SEG13 and RB6/ICSPCLK/ICDCK/SEG14 pins low, while raising the MCLR (VPP) pin from VIL to VIHH. See "PIC16F91X/946 Memory Programming Specification" (DS41244) for more information. RB7 becomes the programming data and the RB6 becomes the programming clock. Both RB7 and RB6 are Schmitt Trigger inputs in this mode. After Reset, to place the device into Program/Verify mode, the Program Counter (PC) is at location 0000h. A 6-bit command is then supplied to the device. Depending on the command, 14 bits of program data are then supplied to or from the device, depending on whether the command was a load or a read. For complete details of serial programming, please refer to the "PIC16F91X/946 Memory Programming Specification" (DS41244). A typical In-Circuit Serial Programming connection is shown in Figure 16-11.
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16.9 In-Circuit Debugger
16.9.1 ICD PINOUT When the debug bit in the Configuration Word register is programmed to a `0', the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB(R) ICD 2. When the microcontroller has this feature enabled, some of the resources are not available for general use. See Table 16-9 for more detail. Note: The user's application must have the circuitry required to support ICD functionality. Once the ICD circuitry is enabled, normal device pin functions on RB6/ICSPCLK/ICDCK/SEG14 and RB7/ICSPDAT/ICDDAT/SEG13 will not be usable. The ICD circuitry uses these pins for communication with the ICD2 external debugger. For more information, see "Using MPLAB(R) ICD 2" (DS51265), available on Microchip's web site (www.microchip.com). The devices in the PIC16F91X/946 family carry the circuitry for the In-Circuit Debugger on-chip and on existing device pins. This eliminates the need for a separate die or package for the ICD device. The pinout for the ICD device is the same as the devices (see Section 1.0 "Device Overview" for complete pinout and pin descriptions). Table 16-9 shows the location and function of the ICD related pins on the 28 and 40-pin devices.
TABLE 16-9:
PIC16F91X/946-ICD PIN DESCRIPTIONS
Pin Numbers TQFP PIC16F946 24 23 36 10, 19, 38, 51 9, 20, 41, 56 26 25 ICDDATA ICDCLK MCLR/VPP VDD VSS AVDD AVSS TTL ST HV P P P P -- -- -- -- -- -- -- In Circuit Debugger Bidirectional data In Circuit Debugger Bidirectional clock Programming voltage Power Ground Analog power Analog ground Name Type Pull-up Description
PDIP PIC16F914/917 40 39 1 11,32 12,31 -- -- Legend: PIC16F913/916 28 27 1 20 8,19 -- --
TTL = TTL input buffer, ST = Schmitt Trigger input buffer, P = Power, HV = High Voltage
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NOTES:
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17.0 INSTRUCTION SET SUMMARY
TABLE 17-1:
Field
f W b k x
The PIC16F913/914/916/917/946 instruction set is highly orthogonal and is comprised of three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 17-1, while the various opcode fields are summarized in Table 17-1. Table 17-2 lists the instructions recognized by the MPASMTM assembler. For byte-oriented instructions, `f' represents a file register designator and `d' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the W register. If `d' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, `b' represents a bit field designator, which selects the bit affected by the operation, while `f' represents the address of the file in which the bit is located. For literal and control operations, `k' represents an 8-bit or 11-bit constant, or literal value. One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution time of 1 s. All instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. All instruction examples use the format `0xhh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit.
OPCODE FIELD DESCRIPTIONS
Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. Program Counter Time-out bit Carry bit Digit carry bit Zero bit Power-down bit
d
PC TO C DC Z PD
FIGURE 17-1:
GENERAL FORMAT FOR INSTRUCTIONS
0
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 8 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 7 k (literal)
0
0
17.1
Read-Modify-Write Operations
Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register. For example, a CLRF PORTA instruction will read PORTA, clear all the data bits, then write the result back to PORTA. This example would have the unintended consequence of clearing the condition that set the RBIF flag.
0
k = 11-bit immediate value
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TABLE 17-2:
Mnemonic, Operands
PIC16F913/914/916/917/946 INSTRUCTION SET
Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C, DC, Z Z Z Z Z Z Z Z Z 1, 2 1, 2 2 1, 2 1, 2 1, 2, 3 1, 2 1, 2, 3 1, 2 1, 2
C C C, DC, Z Z
1, 2 1, 2 1, 2 1, 2 1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: f, b f, b f, b f, b k k k - k k k - k - - k k Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Add literal and W AND literal with W Call Subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 1 (2) 1 (2) 1 1 2 1 2 1 1 2 2 2 1 1 1 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff C, DC, Z Z TO, PD Z 1, 2 1, 2 3 3
LITERAL AND CONTROL OPERATIONS 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk
TO, PD C, DC, Z Z
2: 3:
When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
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17.2
ADDLW Syntax: Operands: Operation: Status Affected: Description:
Instruction Descriptions
Add literal and W [ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z The contents of the W register are added to the eight-bit literal `k' and the result is placed in the W register. k BCF Syntax: Operands: Operation: Status Affected: Description: Bit Clear f [ label ] BCF 0 f 127 0b7 0 (f) None Bit `b' in register `f' is cleared. f,b
ADDWF Syntax: Operands: Operation: Status Affected: Description:
Add W and f [ label ] ADDWF 0 f 127 d [0,1] (W) + (f) (destination) C, DC, Z Add the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
BSF Syntax: Operands: Operation: Status Affected: Description:
Bit Set f [ label ] BSF 0 f 127 0b7 1 (f) None Bit `b' in register `f' is set. f,b
ANDLW Syntax: Operands: Operation: Status Affected: Description:
AND literal with W [ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z The contents of W register are AND'ed with the eight-bit literal `k'. The result is placed in the W register. k
BTFSC Syntax: Operands: Operation: Status Affected: Description:
Bit Test f, Skip if Clear [ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None If bit `b' in register `f' is `1', the next instruction is executed. If bit `b', in register `f', is `0', the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction.
ANDWF Syntax: Operands: Operation: Status Affected: Description:
AND W with f [ label ] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (destination) Z AND the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
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BTFSS Syntax: Operands: Operation: Status Affected: Description: Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None If bit `b' in register `f' is `0', the next instruction is executed. If bit `b' is `1', then the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction. Status Affected: Description: CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
CALL Syntax: Operands: Operation:
Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction.
COMF Syntax: Operands: Operation: Status Affected: Description:
Complement f [ label ] COMF 0 f 127 d [0,1] (f) (destination) Z The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. f,d
Status Affected: Description:
CLRF Syntax: Operands: Operation: Status Affected: Description:
Clear f [ label ] CLRF 0 f 127 00h (f) 1Z Z The contents of register `f' are cleared and the Z bit is set. f
DECF Syntax: Operands: Operation: Status Affected: Description:
Decrement f [ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z Decrement register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'.
CLRW Syntax: Operands: Operation: Status Affected: Description:
Clear W [ label ] CLRW None 00h (W) 1Z Z W register is cleared. Zero bit (Z) is set.
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DECFSZ Syntax: Operands: Operation: Status Affected: Description: Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None The contents of register `f' are decremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', then a NOP is executed instead, making it a 2-cycle instruction. INCFSZ Syntax: Operands: Operation: Status Affected: Description: Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', a NOP is executed instead, making it a 2-cycle instruction.
GOTO Syntax: Operands: Operation: Status Affected: Description:
Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction.
IORLW Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z The contents of the W register are OR'ed with the eight-bit literal `k'. The result is placed in the W register.
INCF Syntax: Operands: Operation: Status Affected: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
IORWF Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z Inclusive OR the W register with register `f'. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
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MOVF Syntax: Operands: Operation: Status Affected: Description: Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (dest) Z The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. 1 1
MOVF FSR, 0
MOVWF Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example:
Move W to f [ label ] (W) (f) None Move data from W register to register `f'. 1 1 MOVW F OPTION MOVWF f 0 f 127
Words: Cycles: Example:
Before Instruction OPTION = W = After Instruction OPTION = W =
0xFF 0x4F 0x4F 0x4F
After Instruction W= value in FSR register Z=1
MOVLW Syntax: Operands: Operation: Status Affected: Description:
Move literal to W [ label ] k (W) None The eight-bit literal `k' is loaded into W register. The "don't cares" will assemble as `0's. 1 1
MOVLW 0x5A
NOP Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example:
No Operation [ label ] None No operation None No operation. 1 1
NOP
MOVLW k
NOP
0 k 255
Words: Cycles: Example:
After Instruction W=
0x5A
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RETFIE Syntax: Operands: Operation: Status Affected: Description: Return from Interrupt [ label ] None TOS PC, 1 GIE None Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. 1 2
RETFIE
RETLW Syntax: Operands: Operation: Status Affected: Description:
Return with literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None The W register is loaded with the eight bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 1 2 CALL TABLE;W contains table
;offset value * ;W now has table value * * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table
RETFIE
Words: Cycles: Example:
Words: Cycles: Example:
After Interrupt PC = GIE =
TABLE TOS 1
Before Instruction W = 0x07 After Instruction W = value of k8
RETURN Syntax: Operands: Operation: Status Affected: Description:
Return from Subroutine [ label ] None TOS PC None Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. RETURN
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RLF Syntax: Operands: Operation: Status Affected: Description: Rotate Left f through Carry [ label ] 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is stored back in register `f'.
C Register f
SLEEP Syntax: Operands: Operation:
Enter Sleep mode [ label ] SLEEP None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped.
RLF
f,d
Status Affected: Description:
Words: Cycles: Example:
1 1
RLF REG1,0 REG1 C = = = = = 1110 0110 0 1110 0110 1100 1100 1
Before Instruction After Instruction
REG1 W C
RRF Syntax: Operands: Operation: Status Affected: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
C Register f
SUBLW Syntax: Operands: Operation: Description:
Subtract W from literal [ label ] SUBLW k 0 k 255 k - (W) (W) The W register is subtracted (2's complement method) from the eight-bit literal `k'. The result is placed in the W register. C=0 C=1 DC = 0 DC = 1 W>k Wk W<3:0> > k<3:0> W<3:0> k<3:0>
Status Affected: C, DC, Z
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SUBWF Syntax: Operands: Operation: Description: Subtract W from f [ label ] SUBWF f,d 0 f 127 d [0,1] (f) - (W) (destination) Subtract (2's complement method) W register from register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f. C=0 C=1 DC = 0 DC = 1 W>f Wf W<3:0> > f<3:0> W<3:0> f<3:0> XORLW Syntax: Operands: Operation: Status Affected: Description: Exclusive OR literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k (W) Z The contents of the W register are XOR'ed with the eight-bit literal `k'. The result is placed in the W register.
Status Affected: C, DC, Z
SWAPF Syntax: Operands: Operation: Status Affected: Description:
Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) None The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed in register `f'.
XORWF Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR W with f [ label ] XORWF 0 f 127 d [0,1] (W) .XOR. (f) (destination) Z Exclusive OR the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
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18.0 DEVELOPMENT SUPPORT
18.1
The PIC(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer - PICkitTM 2 Development Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
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18.2 MPASM Assembler 18.5
The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
MPLAB ASM30 Assembler, Linker and Librarian
MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
18.6
MPLAB SIM Software Simulator
18.3
MPLAB C18 and MPLAB C30 C Compilers
The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
18.4
MPLINK Object Linker/ MPLIB Object Librarian
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
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18.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 18.9 MPLAB ICD 2 In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU STATUS and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices.
The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application.
18.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications.
18.8
MPLAB REAL ICE In-Circuit Emulator System
MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC(R) and MCU devices. It debugs and programs PIC(R) and dsPIC(R) Flash microcontrollers with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high speed, noise tolerant, lowvoltage differential signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.
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18.11 PICSTART Plus Development Programmer
The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant.
18.13 Demonstration, Development and Evaluation Boards
A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart(R) battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest "Product Selector Guide" (DS00148) for the complete list of demonstration, development and evaluation kits.
18.12 PICkit 2 Development Programmer
The PICkitTM 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip's baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH's PICCTM Lite C compiler, and is designed to help get up to speed quickly using PIC(R) microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip's powerful, mid-range Flash memory family of microcontrollers.
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19.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings()
Ambient temperature under bias..........................................................................................................-40 to +125C Storage temperature ........................................................................................................................ -65C to +150C Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V Voltage on MCLR with respect to Vss ............................................................................................... -0.3V to +13.5V Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) ............................................................................................................................... 800 mW Maximum current out of VSS pin ....................................................................................................................... 95 mA Maximum current into VDD pin .......................................................................................................................... 95 mA Input clamp current, IIK (VI < 0 or VI > VDD)................................................................................................................20 mA Output clamp current, IOK (Vo < 0 or Vo >VDD)..........................................................................................................20 mA Maximum output current sunk by any I/O pin.................................................................................................... 25 mA Maximum output current sourced by any I/O pin .............................................................................................. 25 mA Maximum current sourced by all ports (combined) ........................................................................................... 90 mA Maximum current sunk by all ports (combined) ................................................................................................ 90 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL). 2: PORTD and PORTE are not implemented in PIC16F913/916 devices. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
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FIGURE 19-1: PIC16F913/914/916/917/946 VOLTAGE-FREQUENCY GRAPH, -40C TA +125C
5.5 5.0 4.5 VDD (V) 4.0 3.5 3.0 2.5 2.0 0 8 10 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 20
FIGURE 19-2:
HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
125 5% 85 Temperature (C) 2%
60
25
1%
0
2.0
2.5
3.0
3.5
4.0 VDD (V)
4.5
5.0
5.5
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19.1 DC Characteristics: PIC16F913/914/916/917/946-I (Industrial) PIC16F913/914/916/917/946-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. Typ Max. Units 2.0 2.0 3.0 4.5 1.5 -- -- -- -- -- -- VSS 5.5 5.5 5.5 5.5 -- -- V V V V V V Conditions FOSC < = 8 MHz: HFINTOSC, EC FOSC < = 4 MHz FOSC < = 10 MHz FOSC < = 20 MHz Device in Sleep mode See Section 16.2.1 "Power-on Reset (POR)" for details.
DC CHARACTERISTICS Param No. D001 D001C D001D D002* D003 VDR VPOR RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Sym. VDD Characteristic Supply Voltage
D004*
SVDD
0.05
--
--
V/ms See Section 16.2.1 "Power-on Reset (POR)" for details.
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
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19.2 DC Characteristics: PIC16F913/914/916/917/946-I (Industrial) PIC16F913/914/916/917/946-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. -- -- -- D011* -- -- -- D012 -- -- -- D013* -- -- -- D014 -- -- -- D015 -- -- -- D016* -- -- -- D017 -- -- -- D018 -- -- -- D019 -- -- Typ 13 22 33 180 290 490 280 480 0.9 170 280 470 290 490 0.85 8 16 31 416 640 1.13 0.65 1.01 1.86 340 550 0.92 3.8 4.0 Max. 19 30 60 250 400 650 380 670 1.4 295 480 690 450 720 1.3 20 40 65 520 840 1.6 0.9 1.3 2.3 580 900 1.4 4.7 4.8 Units A A A A A A A A mA A A A A A mA A A A A A mA mA mA mA A A mA mA mA Conditions VDD 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 4.5 5.0 FOSC = 20 MHz HS Oscillator mode FOSC = 4 MHz EXTRC mode(3) FOSC = 8 MHz HFINTOSC mode FOSC = 4 MHz HFINTOSC mode FOSC = 31 kHz LFINTOSC mode FOSC = 4 MHz EC Oscillator mode FOSC = 1 MHz EC Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 1 MHz XT Oscillator mode Note FOSC = 32 kHz LP Oscillator mode
DC CHARACTERISTICS Param No. D010
Device Characteristics Supply Current (IDD)(1, 2)
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k.
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19.3 DC Characteristics: PIC16F913/914/916/917/946-I (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Min. -- -- -- -- D021 -- -- -- D022A D022B -- -- -- -- -- D023 -- -- -- D024 -- -- -- D025* -- -- -- D026 -- -- -- D027 -- -- Typ 0.05 0.15 0.35 150 1.0 2.0 3.0 42 85 22 25 33 32 60 120 30 45 75 39 59 98 2.0 2.5 3.0 0.30 0.36 Max. 1.2 1.5 1.8 500 2.2 4.0 7.0 60 122 28 35 45 45 78 160 36 55 95 47 72 124 5.0 5.5 7.0 1.6 1.9 Units A A A nA A A A A A A A A A A A A A A A A A A A A A A Conditions VDD 2.0 3.0 5.0 3.0 2.0 3.0 5.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 A/D Current(1), no conversion in progress T1OSC Current(1), 32.768 kHz CVREF Current(1) (low range) CVREF Current(1) (high range) Comparator Current(1), both comparators enabled PLVD Current BOR Current(1) -40C TA +25C WDT Current(1) Note WDT, BOR, Comparators, VREF and T1OSC disabled
DC CHARACTERISTICS Param No. D020 Device Characteristics Power-down Base Current(IPD)(2)
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
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19.4
DC Characteristics: PIC16F913/914/916/917/946-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C for extended Min. -- -- -- D021E -- -- -- D022E D022B -- -- -- -- -- D023E -- -- -- D024E -- -- -- D025E* -- -- -- D026E -- -- -- D027E -- -- Typ 0.05 0.15 0.35 1 2 3 42 85 22 25 33 32 60 120 30 45 75 39 59 98 3.5 4 5 0.30 0.36 Max. 9 11 15 28 30 35 65 127 48 55 65 45 78 160 70 90 120 91 117 156 18 21 24 12 16 Units A A A A A A A A A A A A A A A A A A A A A A A A A Conditions VDD 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 3.0 5.0 A/D Current(1), no conversion in progress T1OSC Current(1), 32.768 kHz CVREF Current(1) (low range) CVREF Current(1) (high range) Comparator Current(1), both comparators enabled PLVD Current BOR Current(1) WDT Current(1) Note WDT, BOR, Comparators, VREF and T1OSC disabled
DC CHARACTERISTICS Param No. D020E Device Characteristics Power-down Base Current (IPD)(2)
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
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19.5 DC Characteristics: PIC16F913/914/916/917/946-I (Industrial) PIC16F913/914/916/917/946-E (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. Typ Max. Units Conditions
DC CHARACTERISTICS Param No.
Sym.
VIL
Characteristic
Input Low Voltage I/O Port: with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (RC mode) OSC1 (XT mode) OSC1 (HS mode)
(1)
D030 D030A D031 D032 D033 D033A VIH D040 D040A D041 D042 D043 D043A D043B IIL D060 D061 D063 D070* D080 VOH D090 * Note 1: 2: 3: 4: 5: IPUR VOL
Vss Vss Vss VSS VSS VSS
-- -- -- -- -- -- --
0.8 0.15 VDD 0.2 VDD 0.2 VDD 0.3 0.3 VDD
V V V V V V
4.5V VDD 5.5V 2.0V VDD 4.5V 2.0V VDD 5.5V
Input High Voltage I/O ports: with TTL buffer with Schmitt Trigger buffer MCLR OSC1 (XT mode) OSC1 (HS mode) OSC1 (RC mode) Input Leakage Current I/O ports MCLR(3) OSC1 PORTB Weak Pull-up Current Output Low Voltage(5) I/O ports Output High Voltage(5) I/O ports VDD - 0.7 -- -- V IOH = -3.0 mA, VDD = 4.5V (Ind.) -- -- 0.6 V IOL = 8.5 mA, VDD = 4.5V (Ind.)
(2)
2.0 0.25 VDD + 0.8 0.8 VDD 0.8 VDD 1.6 0.7 VDD 0.9 VDD -- -- -- 50
-- -- -- -- -- -- -- 0.1 0.1 0.1 250
VDD VDD VDD VDD VDD VDD VDD 1 5 5 400
V V V V V V V A A A A
4.5V VDD 5.5V 2.0V VDD 4.5V 2.0V VDD 5.5V
(Note 1) VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD VSS VPIN VDD, XT, HS and LP oscillator configuration VDD = 5.0V, VPIN = VSS
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. See Section 13.0 "Data EEPROM and Flash Program Memory Control" for additional information. Including OSC2 in CLKOUT mode.
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19.5 DC Characteristics: PIC16F913/914/916/917/946-I (Industrial) PIC16F913/914/916/917/946-E (Extended) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. Typ Max. Units Conditions
DC CHARACTERISTICS Param No.
Sym.
Characteristic
Capacitive Loading Specs on Output Pins
D101*
COSC2
OSC2 pin
--
--
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1
D101A* CIO D120 D120A D121 ED ED VDRW
All I/O pins Data EEPROM Memory Byte Endurance Byte Endurance VDD for Read/Write
-- 100K 10K VMIN
-- 1M 100K --
50 -- -- 5.5
pF E/W E/W V -40C TA +85C +85C TA +125C Using EECON1 to read/write VMIN = Minimum operating voltage
D122 D123 D124
TDEW TRETD TREF
Erase/Write Cycle Time Characteristic Retention Number of Total Erase/Write Cycles before Refresh(4) Program Flash Memory Cell Endurance Cell Endurance VDD for Read VDD for Erase/Write Erase/Write cycle time Characteristic Retention
-- 40 1M
5 -- 10M
6 -- --
ms Year Provided no other specifications are violated E/W -40C TA +85C
D130 D130A D131 D132 D133 D134
EP ED VPR VPEW TPEW TRETD *
10K 1K VMIN 4.5 -- 40
100K 10K -- -- -- --
-- -- 5.5 5.5 3 --
E/W E/W V V ms
-40C TA +85C +85C TA +125C VMIN = Minimum operating voltage
Year Provided no other specifications are violated
Note 1: 2: 3: 4: 5:
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. See Section 13.0 "Data EEPROM and Flash Program Memory Control" for additional information. Including OSC2 in CLKOUT mode.
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19.6 Thermal Considerations
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. TH01 Symbol JA Characteristic Thermal Resistance Junction to Ambient Typ. 60.0 80.0 90.0 27.5 47.2 46.0 24.4 77.0 31.4 24.0 24.0 20.0 24.7 14.5 20.0 24.4 150 -- -- Units C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C W W Conditions
TH02
TH03 TH04 TH05 TH06 TH07 Note 1: 2: 3:
28-pin PDIP package 28-pin SOIC package 28-pin SSOP package 28-pin QFN 6x6 mm package 40-pin PDIP package 44-pin TQFP package 44-pin QFN 8x8 mm package 64-pin TQFP package JC Thermal Resistance 28-pin PDIP package Junction to Case 28-pin SOIC package 28-pin SSOP package 28-pin QFN 6x6 mm package 40-pin PDIP package 44-pin TQFP package 44-pin QFN 8x8 mm package 64-pin TQFP package TJ Junction Temperature For derated power calculations PD Power Dissipation PD = PINTERNAL + PI/O PINTERNAL Internal Power Dissipation PINTERNAL = IDD x VDD (NOTE 1) PI/O I/O Power Dissipation -- W PI/O = (IOL * VOL) + (IOH * (VDD - VOH)) PDER Derated Power -- W PDER = (TJ - TA)/JA (NOTE 2, 3) IDD is current to run the chip alone without driving any load on the output pins. TA = Ambient Temperature. Maximum allowable power dissipation is the lower value of either the absolute maximum total power dissipation or derated power (PDER).
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19.7 Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F pp cc ck cs di do dt io mc S F H I L Fall High Invalid (High-impedance) Low P R V Z Period Rise Valid High-impedance CCP1 CLKOUT CS SDI SDO Data in I/O port MCLR osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR Frequency T Time Lowercase letters (pp) and their meanings:
Uppercase letters and their meanings:
FIGURE 19-3:
LOAD CONDITIONS
Load Condition
Pin
CL VSS
Legend: CL = 50 pF for all pins 15 pF for OSC2 output
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19.8 AC Characteristics: PIC16F913/914/916/917/946 (Industrial, Extended)
CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
FIGURE 19-4:
OSC1/CLKIN OS02 OS03 OSC2/CLKOUT (LP, XT, HS Modes) OS04 OS04
OSC2/CLKOUT (CLKOUT Mode)
TABLE 19-1:
CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. OS01 Sym. FOSC Characteristic External CLKIN Frequency(1) Min. DC DC DC DC -- 0.1 1 DC 27 250 50 50 -- 250 50 250 Typ -- -- -- -- 32.768 -- -- -- -- -- -- -- 30.5 -- -- -- Max. 37 4 20 20 -- 4 20 4 -- 10,000 1,000 -- Units kHz MHz MHz MHz kHz MHz MHz MHz s ns ns ns s ns ns ns Conditions LP Oscillator mode XT Oscillator mode HS Oscillator mode EC Oscillator mode LP Oscillator mode XT Oscillator mode HS Oscillator mode RC Oscillator mode LP Oscillator mode XT Oscillator mode HS Oscillator mode EC Oscillator mode LP Oscillator mode XT Oscillator mode HS Oscillator mode RC Oscillator mode
Oscillator Frequency(1)
OS02
TOSC
External CLKIN Period(1)
Oscillator Period(1)
200 TCY DC ns TCY = 4/FOSC 2 -- -- s LP oscillator 100 -- -- ns XT oscillator 20 -- -- ns HS oscillator OS05* TosR, External CLKIN Rise, 0 -- ns LP oscillator TosF External CLKIN Fall 0 -- ns XT oscillator 0 -- ns HS oscillator * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices.
OS03 OS04*
TCY TosH, TosL
Instruction Cycle Time(1) External CLKIN High, External CLKIN Low
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TABLE 19-2: OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. OS06 OS07 OS08 Sym. TWARM TSC HFOSC Characteristic Internal Oscillator Switch when running(3) Fail-Safe Sample Clock Period(1) Internal Calibrated HFINTOSC Frequency(2) Freq. Tolerance -- -- 1% 2% 5% Min. -- -- 7.92 7.84 7.60 Typ -- 21 8.0 8.0 8.0 Max. 2 -- 8.08 8.16 8.40 Units TOSC ms MHz MHz MHz Conditions Slowest clock LFINTOSC/64 VDD = 3.5V, 25C 2.5V VDD 5.5V, 0C TA +85C 2.0V VDD 5.5V, -40C TA +85C (Ind.), -40C TA +125C (Ext.)
OS09* OS10*
LFOSC TIOSC
ST
Internal Uncalibrated LFINTOSC Frequency HFINTOSC Oscillator Wake-up from Sleep Start-up Time
-- -- -- --
15 5.5 3.5 3
31 12 7 6
45 24 14 11
kHz s s s VDD = 2.0V, -40C to +85C VDD = 3.0V, -40C to +85C VDD = 5.0V, -40C to +85C
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to the OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 3: By design.
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FIGURE 19-5:
Cycle
CLKOUT AND I/O TIMING
Write Q4 Fetch Q1 Read Q2 Execute Q3
FOSC OS11 CLKOUT OS19 OS13 I/O pin (Input) OS15 I/O pin (Output) Old Value OS18, OS19 OS14 New Value OS17 OS20 OS21 OS16 OS18 OS12
TABLE 19-3:
CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. OS11 OS12 OS13 OS14 OS15* OS16 OS17 OS18 OS19 OS20* OS21* * Note 1: 2: Symbol TOSH2CKL TOSH2CKH TCKL2IOV TIOV2CKH TOSH2IOV TOSH2IOI TIOV2OSH TIOR TIOF TINP TRAP Characteristic FOSC to CLKOUT (1) FOSC to CLKOUT
(1)
Min. -- -- -- TOSC + 200 ns -- 50 20 -- -- -- -- 25 TCY
Typ Max. Units -- -- -- -- 50 -- -- 15 40 28 15 -- -- 70 72 20 -- 70 -- -- 72 32 55 30 -- -- ns ns ns ns ns ns ns ns ns ns ns
Conditions VDD = 5.0V VDD = 5.0V
CLKOUT to Port out valid(1) Port input valid before CLKOUT(1) FOSC (Q1 cycle) to Port out valid FOSC (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to FOSC (Q2 cycle) (I/O in setup time) Port output rise time(2) Port output fall time(2) INT pin input high or low time PORTA interrupt-on-change new input level time
VDD = 5.0V VDD = 5.0V
VDD = 2.0V VDD = 5.0V VDD = 2.0V VDD = 5.0V
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. Includes OSC2 in CLKOUT mode.
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FIGURE 19-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR PWRT Time-out OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 34 I/O pins Note 1: Asserted low. 31 34 33 32 30
FIGURE 19-7:
VDD
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VBOR
VBOR + VHYST
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
33*
BOR Reset (if PWRTE = 1) BOR Reset (if PWRTE = 0)
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TABLE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param Symbol No. 30 31 32 33* 34* TMCL TWDT TOST TPWRT TIOZ Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period(1, 2) Power-up Timer Period I/O High-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Voltage Brown-out Reset Hysteresis Brown-out Reset Minimum Detection Period Min. 2 5 10 10 -- 40 -- Typ -- -- 16 16 1024 65 -- Max. Units -- -- 29 31 -- 140 2.0 s s ms ms Conditions VDD = 5V, -40C to +85C VDD = 5V VDD = 5V, -40C to +85C VDD = 5V
TOSC (NOTE 3) ms s
35 36* 37*
VBOR VHYST TBOR
2.0 2.0 -- 100
-- -- 50 --
2.2 2.25 -- --
V V mV s
-40C to +85C, (NOTE 4) -40C to +125C, (NOTE 4) VDD VBOR
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to the OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2: By design. 3: Period of the slower clock. 4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended.
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FIGURE 19-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI 40 42 41
T1CKI 45 47 TMR0 or TMR1 46 49
TABLE 19-5:
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. 40* 41* 42* Symbol TT0H TT0L TT0P Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler Min. 0.5 TCY + 20 10 0.5 TCY + 20 10 Greater of: 20 or TCY + 40 N 0.5 TCY + 20 15 30 0.5 TCY + 20 15 30 Greater of: 30 or TCY + 40 N 60 -- 2 TOSC Typ -- -- -- -- -- Max. -- -- -- -- -- Units ns ns ns ns ns N = prescale value (2, 4, ..., 256) Conditions
45*
TT1H
T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler Asynchronous T1CKI Low Time Synchronous, No Prescaler Synchronous, with Prescaler Asynchronous
-- -- -- -- -- -- --
-- -- -- -- -- -- --
ns ns ns ns ns ns ns N = prescale value (1, 2, 4, 8)
46*
TT1L
47*
TT1P
T1CKI Input Synchronous Period Asynchronous
-- 32.768 --
-- -- 7 TOSC
ns kHz -- Timers in Sync mode
48 49*
FT1
Timer1 Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN)
TCKEZTMR1 Delay from External Clock Edge to Timer Increment *
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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TABLE 19-6: COMPARATOR SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. CM01 CM02 Symbol VOS VCM Characteristics Input Offset Voltage Input Common Mode Voltage Common Mode Rejection Ratio Response Time Falling Rising CM05* TMC2COV Comparator Mode Change to Output Valid Min. -- 0 +55 -- -- -- Typ 5.0 -- -- 150 200 -- Max. 10 VDD - 1.5 -- 600 1000 10 Units mV V dB ns ns s (NOTE 1) Comments (VDD - 1.5)/2
CM03* CMRR CM04* TRT
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Response time is measured with one comparator input at (VDD - 1.5)/2 - 100 mV to (VDD - 1.5)/2 + 20 mV.
TABLE 19-7:
COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param Symbol No. CV01* CV02* CV03* CV04* CLSB CACC CR CST Characteristics Step Size(2) Absolute Accuracy Unit Resistor Value (R) Settling Time(1) Min. -- -- -- -- -- -- Typ VDD/24 VDD/32 -- -- 2k -- Max. -- -- 1/2 1/2 -- 10 Units V V LSb LSb s Comments Low Range (VRR = 1) High Range (VRR = 0) Low Range (VRR = 1) High Range (VRR = 0)
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from `0000' to `1111'. 2: See Section 8.10 "Comparator Voltage Reference" for more information.
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TABLE 19-8: PIC16F913/914/916/917/946 A/D CONVERTER (ADC) CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param Sym. No. AD01 AD02 AD03 AD04 AD07 NR EIL EDL EOFF EGN Characteristic Resolution Integral Error Differential Error Offset Error Gain Error Reference Voltage
(1)
Min. -- -- -- -- -- 2.2 2.7 VSS --
Typ -- -- -- -- -- --
Max. 10 bits 1 1 1 1 VDD VDD VREF 10
Units bit
Conditions
LSb VREF = 5.12V LSb No missing codes to 10 bits VREF = 5.12V LSb VREF = 5.12V LSb VREF = 5.12V V Absolute minimum to ensure 1 LSb accuracy V k
AD06 VREF AD06A AD07 AD08 VAIN ZAIN
Full-Scale Range Recommended Impedance of Analog Voltage Source VREF Input Current(1)
-- --
AD09* IREF
10 --
-- --
1000 50
A A
During VAIN acquisition. Based on differential of VHOLD to VAIN. During A/D conversion cycle.
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADC VREF is from external VREF or VDD pin, whichever is selected as reference input.
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TABLE 19-9: PIC16F913/914/916/917/946 A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param Sym. No. AD130* TAD Characteristic A/D Clock Period A/D Internal RC Oscillator Period AD131 TCNV Conversion Time (not including Acquisition Time)(1) Min. 1.6 3.0 3.0 1.6 -- Typ -- -- 6.0 4.0 11 Max. Units 9.0 9.0 9.0 6.0 -- s s s s TAD Conditions TOSC-based, VREF 3.0V TOSC-based, VREF full range ADCS<1:0> = 11 (ADRC mode) At VDD = 2.5V At VDD = 5.0V Set GO/DONE bit to new data in A/D Result register
AD132* TACQ Acquisition Time AD133* TAMP Amplifier Settling Time AD134 TGO Q4 to A/D Clock Start -- -- --
11.5 -- TOSC/2 TOSC/2 + TCY
-- 5 -- --
s s -- -- If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle. 2: See Section 12.3 "A/D Acquisition Requirements" for minimum conditions.
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FIGURE 19-9: PIC16F913/914/916/917/946 A/D CONVERSION TIMING (NORMAL MODE)
1 TCY AD131 AD130 A/D CLK A/D Data ADRES ADIF GO Sample Note 1: AD132 Sampling Stopped 9 8 OLD_DATA 7 6 3 2 1 0 NEW_DATA 1 TCY DONE BSF ADCON0, GO AD134 Q4 (TOSC/2(1))
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
FIGURE 19-10:
PIC16F913/914/916/917/946 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO AD134 Q4 A/D CLK A/D Data ADRES ADIF GO Sample AD132 Sampling Stopped 9 8 7 6 3 2 1 0 NEW_DATA 1 TCY DONE (TOSC/2 + TCY(1)) AD131 AD130 1 TCY
OLD_DATA
Note 1:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
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FIGURE 19-11:
RC6/TX/CK SCK/SCL/SEG9 121 RC7/RX/DT/ SDI/SDA/SEG8 120 Note: Refer to Figure 19-3 for load conditions. 122 121
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 19-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param. No. 120 121 122 Symbol TCKH2DT V TCKRF TDTRF Characteristic SYNC XMIT (Master and Slave) Clock high to data-out valid Clock out rise time and fall time (Master mode) Data-out rise time and fall time 3.0-5.5V 2.0-5.5V 3.0-5.5V 2.0-5.5V 3.0-5.5V 2.0-5.5V Min. -- -- -- -- -- -- Max. 80 100 45 50 45 50 Units ns ns ns ns ns ns Conditions
FIGURE 19-12:
RC6/TX/CK SCK/SCL/SEG9 RC7/RX/DT/ SDI/SDA/SEG8
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
125
126 Note: Refer to Figure 19-3 for load conditions.
TABLE 19-11: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param. No. 125 126 Symbol Characteristic Min. 10 15 Max. -- -- Units ns ns Conditions
TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK (DT hold time) TCKL2DTL Data-hold after CK (DT hold time)
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FIGURE 19-13: CAPTURE/COMPARE/PWM TIMINGS
CCP1/CCP2 (Capture mode) 50 52 CCP1/CCP2 (Compare mode) 53 Note: Refer to Figure 19-3 for load conditions. 54 51
TABLE 19-12: CAPTURE/COMPARE/PWM (CCP) REQUIREMENTS
Param. Sym. Characteristic No. 50* TCCL CCPx input low time No Prescaler With Prescaler No Prescaler With Prescaler 3.0-5.5V 2.0-5.5V 52* 53* 54* TCCP CCPx input period TCCR CCPx output fall time TCCF CCPx output fall time 3.0-5.5V 2.0-5.5V 3.0-5.5V 2.0-5.5V 3.0-5.5V 2.0-5.5V 51* TCCH CCPx input high time Min. 0.5TCY + 5 10 20 0.5TCY + 5 10 20 3TCY + 40 N -- -- -- -- Typ Max. Units Conditions -- -- -- -- -- -- -- 10 25 10 25 -- -- -- -- -- -- -- 25 50 25 45 ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1,4 or 16)
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested.
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TABLE 19-13: PIC16F913/914/916/917/946 PLVD CHARACTERISTICS:
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Operating Voltage VDD Range 2.0V-5.5V Min. 1.900 2.000 2.100 2.200 3.825 4.025 4.425 -- Typ 2.0 2.1 2.2 2.3 4.0 4.2 4.5 50 25 Max. (85C) 2.100 2.200 2.300 2.400 4.175 4.375 4.675 -- Max. (125C) 2.125 2.225 2.325 2.425 4.200 4.400 4.700 -- Units V V V V V V V s VDD = 5.0V VDD = 3.0V Conditions
Sym. VPLVD PLVD Voltage
Characteristic LVDL<2:0> = 001 LVDL<2:0> = 010 LVDL<2:0> = 011 LVDL<2:0> = 100 LVDL<2:0> = 101 LVDL<2:0> = 110 LVDL<2:0> = 111
*TPLVDS PLVD Settling time
* These parameters are characterized but not tested Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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FIGURE 19-14:
SS 70 SCK (CKP = 0) 71 72 78 79
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SCK (CKP = 1) 79 MSb 75, 76 SDI MSb In 74 73 Note: Refer to Figure 19-3 for load conditions. bit 6 - - - -1 LSb In bit 6 - - - - - -1 78 LSb
80 SDO
FIGURE 19-15:
SS
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
81 SCK (CKP = 0) 71 73 SCK (CKP = 1) 72 79
80 78 MSb 75, 76 bit 6 - - - - - -1 LSb
SDO
SDI
MSb In 74
bit 6 - - - -1
LSb In
Note: Refer to Figure 19-3 for load conditions.
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FIGURE 19-16:
SS 70 SCK (CKP = 0) 71 72 78 79 83
SPI SLAVE MODE TIMING (CKE = 0)
SCK (CKP = 1) 79 MSb 75, 76 SDI 73 Note: Refer to Figure 19-3 for load conditions. MSb In 74 bit 6 - - - -1 LSb In bit 6 - - - - - -1 78 LSb 77
80 SDO
FIGURE 19-17:
SS
SPI SLAVE MODE TIMING (CKE = 1)
82
SCK (CKP = 0)
70 83 71 72
SCK (CKP = 1) 80
SDO
MSb 75, 76
bit 6 - - - - - -1
LSb 77
SDI
MSb In 74
bit 6 - - - -1
LSb In
Note: Refer to Figure 19-3 for load conditions.
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TABLE 19-14: SPI MODE REQUIREMENTS
Param No. 70* 71* 72* 73* 74* 75* 76* 77* 78* 79* 80* 81* 82* 83* Symbol Characteristic Min. TCY TCY + 20 TCY + 20 100 100 -- -- -- 10 -- -- -- 3.0-5.5V 2.0-5.5V -- -- Tcy -- 1.5TCY + 40 3.0-5.5V 2.0-5.5V Typ -- -- -- -- -- 10 25 10 -- 10 25 10 -- -- -- -- -- Max. Units Conditions -- -- -- -- -- 25 50 25 50 25 50 25 50 145 -- 50 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TSSL2SCH, SS to SCK or SCK input TSSL2SCL TSCH TSCL SCK input high time (Slave mode) SCK input low time (Slave mode)
TDIV2SCH, Setup time of SDI data input to SCK edge TDIV2SCL TSCH2DIL, TSCL2DIL TDOR TDOF TSSH2DOZ TSCR TSCF Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SS to SDO output high-impedance SCK output rise time (Master mode) SCK output fall time (Master mode) 3.0-5.5V 2.0-5.5V
TSCH2DOV, SDO data output valid after TSCL2DOV SCK edge
TDOV2SCH, SDO data output setup to SCK edge TDOV2SCL TSSL2DOV SDO data output valid after SS edge TSCH2SSH, SS after SCK edge TSCL2SSH
* These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 19-18:
I2CTM BUS START/STOP BITS TIMING
SCL 90 SDA
91 92
93
Start Condition Note: Refer to Figure 19-3 for load conditions.
Stop Condition
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TABLE 19-15: I2CTM BUS START/STOP BITS REQUIREMENTS
Param No. 90* 91* 92* 93 * Symbol TSU:STA THD:STA TSU:STO Characteristic Start condition Setup time Start condition Hold time Stop condition Setup time 400 kHz mode 400 kHz mode 400 kHz mode 400 kHz mode Min. 600 600 600 600 Typ. Max. Units -- -- -- -- -- -- -- -- ns ns ns ns Conditions Only relevant for Repeated Start condition After this period, the first clock pulse is generated
THD:STO Stop condition Hold time
These parameters are characterized but not tested.
FIGURE 19-19:
I2CTM BUS DATA TIMING
103 100 101 102
SCL
90 91
106
107 92
SDA In 109 SDA Out Note: Refer to Figure 19-3 for load conditions. 109 110
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TABLE 19-16: I2CTM BUS DATA REQUIREMENTS
Param. No. 100* 101* 102* 103* 90* 91* 106* 107* 92* 109* 110* Symbol THIGH TLOW TR TF TSU:STA THD:STA THD:DAT TSU:DAT TSU:STO TAA TBUF Characteristic Clock high time Clock low time SDA and SCL rise time 400 kHz mode SSP Module 400 kHz mode SSP Module 400 kHz mode Min. 0.6 1.5TCY 1.3 1.5TCY 20 + 0.1CB 20 + 0.1CB 1.3 0.6 0 100 0.6 -- 1.3 Max. -- -- -- -- 250 250 -- -- 0.9 -- -- -- -- ns ns s s s ns s ns s (Note 1) Time the bus must be free before a new transmission can start (Note 2) s Units s Conditions Device must operate at a minimum of 10 MHz Device must operate at a minimum of 10 MHz CB is specified to be from 10-400 pF CB is specified to be from 10-400 pF Only relevant for Repeated Start condition After this period the first clock pulse is generated
SDA and SCL fall time 400 kHz mode Start condition setup time Start condition hold time Data input hold time Data input setup time Stop condition setup time Output valid from clock Bus free time 400 kHz mode 400 kHz mode 400 kHz mode 400 kHz mode 400 kHz mode 400 kHz mode 400 kHz mode
CB * Note 1: 2:
Bus capacitive loading
--
400
pF
These parameters are characterized but not tested. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released.
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20.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
"Typical" represents the mean of the distribution at 25C. "Maximum" or "minimum" represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over each temperature range. FIGURE 20-1: TYPICAL IDD vs. FOSC OVER VDD (EC Typical 2V 3V 4V 5V EC 1Mhz 0.086 0.153 0.220 Mode0.277 2Mhz 0.150 0.2596 0.3718 0.4681 4Mhz 0.279 0.472 0.675 0.850 4.0 6Mhz 0.382 0.635 0.903 1.135 8Mhz Typical: Statistical Mean @25C 0.486 0.798 1.132 1.420 10Mhz Maximum: Mean (Worst-case Temp) + 3 0.589 0.961 1.360 1.706 3.5 12Mhz 0.696 1.126 1.596 2.005 (-40C to 125C) 14Mhz 0.802 1.291 1.832 2.304 16Mhz 0.908 1.457 2.068 2.603 3.0 18Mhz 1.017 1.602 2.268 2.848 20Mhz 1.126 1.748 2.469 3.093 2.5
Max IDD (mA) 2.0 1Mhz 2Mhz 4Mhz 1.5 6Mhz 8Mhz 1.0 10Mhz 12Mhz 14Mhz 0.5 16Mhz 18Mhz 20Mhz 0.0 1 MHz 2V 0.168 0.261 0.449 0.577 0.705 0.833 0.956 1.078 1.201 1.305 1.409 2 MHz 3V 0.236 0.394 0.710 0.972 1.233 1.495 1.711 1.926 2.142 2.326 2.510 4 MHz 6 MHz 4V 0.315 0.537 0.981 1.331 1.682 2.032 2.372 2.713 3.054 3.295 3.536 8 MHz 5V 0.412 0.704 1.287 1.739 2.191 2.642 3.101 3.560 4.018 4.324 4.630 10 MHz VDD (V)
MODE) 5.5V
0.310 0.5236 0.951 1.269 1.587 1.905 2.241 2.577 2.913 3.185 3.458
5.5V 5V
4V 5.5V 0.452 0.780 1.435 1.950 2.465 2.979 3.506 4.032 4.558 4.887 12 MHz 14 MHz 16 MHz 18 MHz
3V
2V
20 MHz
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FIGURE 20-2:
6.0 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C) 5.5V 5V
MAXIMUM IDD vs. FOSC OVER VDD (EC MODE)
5.0
4.0 4V IDD (mA) 3.0 3V 2.0 2V 1.0
0.0 1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz VDD (V) 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz
FIGURE 20-3:
5.0 4.5 4.0 3.5 IDD (mA) 3.0 2.5 2.0 1.5 1.0 0.5 0.0
TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
HS Mode
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
5.5V 5V 4.5V
3V 3.5V 4V 4.5V 5V 5.5V 0.567660978 0.6909750.8211857610.9883470541.0462473761.119615457 1.1610564131.4069334781.6664380432.0030751092.1193190652.268818804 4V 2.883088587 3.03554863 3.23775 3.5V 3.74139 3.967407543 3V
4 MHz
10 MHz FOSC
16 MHz
20 Mhz
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FIGURE 20-4:
5.5 5.0 4.5 4.0 3.5 IDD (mA) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4 MHz 10 MHz FOSC 16 MHz 20 MHz 4V 3.5V 3V Typical: Statistical 3.5V @25C Mean 3V 4V 4.5V 5V 5.5V Maximum: Mean (Worst-case Temp) + 3 0.8868608641.0693043161.2645617521.4868166111.5076394231.520959608 (-40C1.6176371031.9623642592.3355493582.7630868222.8139211682.849632041 to 125C) 3.8375797553.9157601913.967889512 4.685048474 4.78069621 5.5V 5V 4.5V
MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) HS Mode
FIGURE 20-5:
TYPICAL IDD vs. VDD OVER FOSC (XT MODE)
XT Mode
1,200
1,000
Typical: Statistical Mean @25xC 180.1774 235.0683 289.9592 Maximum: Mean (Worst Case Temp) + 3 283.7333 382.484 481.2347 (-40xC to 125xC)
Typical: Statistical Mean @25C 337.753 385.547 436.866 488.184 554.8964 Maximum: Mean (Worst-case Temp) + 3 674.6106 783.831 893.052 1033.15 577.923 (-40C to 125C)
Vdd 2 2.5 3 3.5 4 4.5 5 5.5 244.8837 320.7132 396.5426 461.707 526.8719 587.642 648.412 724.0755 375.529 522.3721 669.2152 822.619 976.0232 1163.67 1351.32
2
2.5
3
3.5
4
4.5
5
5.5
800 IDD (uA)
600
4 MHz
400 1 MHz 200
0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
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FIGURE 20-6: MAXIMUM IDD vs. VDD OVER FOSC (XT MODE)
XT Mode 1,800 1,600 1,400 1,200 IDD (uA) 1,000 800 600 400 200 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 1 MHz 4 MHz Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
FIGURE 20-7:
TYPICAL IDD vs. VDD OVER FOSC (EXTRC MODE)
(EXTRC Mode)
1,800 1,600 1,400 1,200 IDD (uA) 1,000 800 1 Mhz 600 400 200 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 4 Mhz Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
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FIGURE 20-8:
2,000 1,800 1,600 1,400 1,200 IDD (uA) 1,000 800 600 400 200 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 1 Mhz Typical: Statistical Mean @25C Typical: Statistical Mean @25xC Maximum: Mean (Worst Case Temp) 3 Maximum: Mean (Worst-case Temp) + + 3 (-40xC to 125xC) (-40C to 125C)
MAXIMUM IDD vs. VDD (EXTRC MODE)
4 Mhz
FIGURE 20-9:
80 70 60 50 IDD (A) 40 30 20 10 0 2.0
IDD vs. VDD OVER FOSC (LFINTOSC MODE, 31 kHz)
LFINTOSC Mode, 31KHZ
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
Maximum
Typical
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
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FIGURE 20-10:
80 70 60 IDD (uA) 50 40 30 20 10 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 32 kHz Typical Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
IDD vs. VDD (LP MODE)
32 kHz Maximum
FIGURE 20-11:
2,500
TYPICAL IDD vs. FOSC OVER VDD (HFINTOSC MODE)
4V HFINTOSC 5V 5.5V
2,000
197.9192604299.82617395.019 496.999 574.901 210.9124688 324.4079 431.721 544.182 620.66 Typical: Statistical Mean @25xC Typical: Statistical Mean @25C Maximum: Mean (Worst Case Temp) + 3 239.9707708369.77809491.538 623.314 717.723 Maximum: Mean (Worst-case Temp) + 3 (-40xC to 125xC) 298.6634479460.30461619.714 793.635 901.409 (-40C to 125C) 414.3997292639.99889 878.13 1127.53 1275.6 649.86985881014.40021421.21 1858.97 2097.71
5.5V 5V
IDD (uA)
1,500
4V 3V 2V
1,000
500 2V 0 125 kHz 25 kHz 500 kHz 1 MHz VDD (V) 2 MHz 4 MHz 8 MHz 3V 4V 5V 5.5V
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FIGURE 20-12:
3,000 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C) 5.5V
MAXIMUM IDD vs. FOSC OVER VDD (HFINTOSC MODE)
HFINTOSC
2,500
5V 2,000 IDD (uA) 4V 1,500 3V 1,000 2V
500
0 125 kHz 250 kHz 500 kHz 1 MHz VDD (V) 2 MHz 4 MHz 8 MHz
FIGURE 20-13:
TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Typical
(Sleep Mode all Peripherals Disabled)
0.45 0.40 0.35 0.30
IPD (uA)
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
0.25 0.20 0.15 0.10 0.05 0.00 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
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FIGURE 20-14:
18 16 14 Max. 125C 12 IPD (A) 10 8 6 4 2 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 Max. 85C Typical: Statistical Mean @25C Maximum: Mean + 3 Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
Maximum (Sleep Mode all Peripherals Disabled)
FIGURE 20-15:
COMPARATOR IPD vs. VDD (BOTH COMPARATORS ENABLED)
180 160 140 120 Maximum IPD (uA) 100 80 60 Typical Max 31.9 40 43.9 45.6 60.8 59.3 20 77.7 73.0 95.8 86.7 113.8 0131.8 100.4 114.1 149.9 2.0 127.7 Typical Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
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FIGURE 20-16:
180 160 140 120 100 80 60 40 20 0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 Typical 35.0 44.4 56.2 68.1 79.9 91.7 104.1 Max 51.1 65.0 82.5 100.0 117.5 135.1 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
BOR IPD vs. VDD OVER TEMPERATURE
IPD (uA)
Maximum 2.5 3 3.5 4 4.5 5 5.5
Typical
FIGURE 20-17:
3.0
TYPICAL WDT IPD vs. VDD (25C)
2.5
2.0 IPD (uA)
1.5
Typical: Statistical Mean 85xC Max 125xC Typical Max @25C 2 1.007 2.140 27.702 2.5 1.146 2.711 29.079 3 1.285 3.282 30.08 3.5 1.449 3.899 31.347 4 1.612 4.515 32.238 4.5 1.924 5.401 33.129 5 2.237 6.288 34.02 5.5 2.764 7.776
1.0
0.5
0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
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FIGURE 20-18:
40.0 35.0 30.0 25.0 IPD (uA) 20.0 15.0 10.0 5.0 0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 Max. 85C Maximum: Mean + Maximum: Mean + 33 Max. 125C
MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE
FIGURE 20-19:
32 30 28 26 24 Time (ms) 22 20
WDT PERIOD vs. VDD OVER TEMPERATURE
WDT Time-out Period
Maximum: Mean + 3 (-40C to 125C) Max. (125C) Max. (85C)
Typical 18 16 14 12 10 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 Minimum
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FIGURE 20-20:
30 28 26 24 22 20 18 16 14 12 10 -40C 25C Temperature (C) 85C 125C Minimum Maximum Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3
WDT PERIOD vs. TEMPERATURE (VDD = 5.0V)
Vdd = 5V
Time (ms)
Typical
FIGURE 20-21:
CVREF IPD vs. VDD OVER TEMPERATURE (HIGH RANGE)
High Range
140 Max 85xC Max 125xC 35.8 68.0 Typical: Statistical Mean @25C 44.8 77.3 Maximum: Mean (Worst-case Temp) + 3 53.8 86.5 120 (-40C to 125C) 62.8 94.3 71.8 102.1 81.0 109.8 100 Max. 125C 90.1 117.6 99.2 125.1 IPD (uA) 80 Max. 85C 60 Typical
40 Max 85xC Max 125xC 46.5 86.4 58.3 98.1 70.0 109.9 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
20
0
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FIGURE 20-22:
180 160 140 Max. 125C 120 IPD (uA) 100 Max. 85C 80 Typical 60 40 20 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
CVREF IPD vs. VDD OVER TEMPERATURE (LOW RANGE)
low Range
FIGURE 20-23:
LVD IPD vs. VDD OVER TEMPERATURE
80 70 60 50 IPD (uA) Max. 85C 40 30 Typical 20 10 0 2.0V 2.5V 3.0V 3.5V VDD (V) 4.0V 4.5V 5V 5.5V Typical: Statistical Mean @25C Maximum: Mean + 3 Max. 125C
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FIGURE 20-24:
30 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C) Max. 125C 20 IPD (uA)
T1OSC IPD vs. VDD OVER TEMPERATURE (32 kHz)
25
15 2 2.5 3 3.5 4 4.5 5 5.5 Typ 25xC 2.022 2.247 2.472 2.453 2.433 2.711 2.989 3.112 Max 85xC 4.98 5.23 5.49 5.79 6.08 6.54 7.00 7.34 Max 125xC 17.54 19.02 20.29 21.50 Max. 85C 22.45 23.30 24.00 Typ. 25C
10
5
0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 20-25:
VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)
(VDD = 3V, -40xC TO 125xC)
0.8 Typical: Statistical Mean @25C Maximum: Mean + 3 Max. 125C 0.6
0.7
0.5 VOL (V)
Max. 85C
0.4 Typical 25C
0.3
0.2 Min. -40C 0.1
0.0 5.0 5.5 6.0 6.5 7.0 7.5 IOL (mA) 8.0 8.5 9.0 9.5 10.0
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FIGURE 20-26:
0.45 0.40 0.35 Max. 85C 0.30 0.25 Typ. 25C 0.20 0.15 0.10 0.05 0.00 5.0 5.5 6.0 6.5 7.0 7.5 IOL (mA) 8.0 8.5 9.0 9.5 10.0 Typical: Statistical Mean @25C Typical: Statistical Maximum: Mean + 3 Mean Maximum: Means + 3
VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V)
Max. 125C
VOL (V)
Min. -40C
FIGURE 20-27:
3.5
VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)
3.0
Max. -40C Typ. 25C
2.5
Min. 125C 2.0 VOH (V)
1.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
1.0
0.5
0.0 0.0 -0.5 -1.0 -1.5 -2.0 IOH (mA) -2.5 -3.0 -3.5 -4.0
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FIGURE 20-28:
5.5
VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V) ( , )
5.0 Max. -40C
Typ. 25C 4.5 VOH (V) Min. 125C
4.0
3.5
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
3.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 IOH (mA) -3.0 -3.5 -4.0 -4.5 -5.0
FIGURE 20-29:
1.7
TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
(TTL Input, -40xC TO 125xC)
1.5
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C) Max. -40C
1.3 VIN (V)
Typ. 25C 1.1 Min. 125C 0.9
0.7
0.5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
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FIGURE 20-30:
4.0 VIH Max. 125C 3.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
(ST Input, -40xC TO 125xC)
VIH Min. -40C
3.0
VIN (V)
2.5
2.0 VIL Max. -40C 1.5 VIL Min. 125C
1.0
0.5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 20-31:
4 5.5 1,000 900 800 Response Time (nS) 700 600 500 400 300 200 100 0
200 278 639 846 V+ = VCM 531 140 input 202 V- input = Transition from VCM + 100MV to VCM - 20MV
COMPARATOR RESPONSE TIME (RISING EDGE)
Max. (125C)
Note:
VCM = VDD - 1.5V)/2 V+ input = VCM V- input = Transition from VCM + 100MV to VCM - 20MV
Max. (85C)
Typ. (25C) Min. (-40C)
2.0
2.5 VDD (Volts)
4.0
5.5
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FIGURE 20-32:
Vdd -40xC 25xC 85xC 125xC 2 279 327 547 557 600 2.5 226 267 425 440 4 172 204 304 319 5.5 119 142 182 500
COMPARATOR RESPONSE TIME (FALLING EDGE)
Response Time (nS)
400
300
200 Note: 100 VCM = VDD - 1.5V)/2 V+ input = VCM V- input = Transition from VCM - 100MV to VCM + 20MV
Max. (125C) Max. (85C) Typ. (25C) Min. (-40C)
0 2.0 2.5 VDD (Volts) 4.0 5.5
FIGURE 20-33:
45,000 40,000 35,000 30,000 Frequency (Hz) 25,000 20,000 15,000 10,000 5,000 0 2.0
LFINTOSC FREQUENCY vs. VDD OVER TEMPERATURE (31 kHz)
LFINTOSC 31Khz
Max. -40C
Typ. 25C
Min. 85C Min. 125C
Typical: Statistical Mean @25C Maximum: Mean (Worst-case) + 3
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
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FIGURE 20-34:
8 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
ADC CLOCK PERIOD vs. VDD OVER TEMPERATURE
125C 6
85C
Time (s)
4
25C
-40C 2
0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 20-35:
16 14 85C 12 25C 10 Time (s) -40C 8 6 4 2 0 2.0
TYPICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
Typical: Statistical Mean @25C Maximum: Mean (Worst-case) + 3
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
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FIGURE 20-36:
25
MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
-40C to +85C
20
Typical: Statistical Mean @25C Maximum: Mean (Worst-case) + 3
Time (s)
15 85C 25C 10 -40C
5
0 2.0
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
FIGURE 20-37:
10 9 8 7 6
MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
-40C to +85C
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 85C 25C
Time (s)
5 -40C 4 3 2 1 0 2.0
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
(c) 2007 Microchip Technology Inc.
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FIGURE 20-38:
5 4 3 Change from Calibration (%) 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25C)
FIGURE 20-39:
5 4 3 Change from Calibration (%) 2 1 0 -1 -2 -3 -4 -5 2.0
TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE VDD (85C)
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
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FIGURE 20-40:
5 4 3 Change from Calibration (%) 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125C)
FIGURE 20-41:
5 4 3 Change from Calibration (%) 2 1 0 -1 -2 -3 -4 -5 2.0
TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40C)
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
(c) 2007 Microchip Technology Inc.
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NOTES:
DS41250F-page 304
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21.0
21.1
PACKAGING INFORMATION
Package Marking Information
28-Lead SPDIP
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC16F913 -I/SP e3 0710017
40-Lead PDIP
XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC16F914 -I/P e3 0710017
28-Lead QFN
Example
XXXXXXXX XXXXXXXX YYWWNNN
16F916 -I/ML e3 0710017
Legend: XX...X Y YY WW NNN
e3
* Note:
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
*
Standard PIC(R) device marking consists of Microchip part number, year code, week code and traceability code. For PIC(R) device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
(c) 2007 Microchip Technology Inc.
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Package Marking Information (Continued)
44-Lead QFN Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PIC16F914 -I/ML e3 0710017
28-Lead SOIC
XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC16F913 -I/SO e3 0710017
28-Lead SSOP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
Example PIC16F916 -I/SS e3 0710017
44-Lead TQFP
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PIC16F917 -I/PT e3 0710017
64-Lead TQFP (10x10x1mm)
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PIC16F946 -I/PT e3 0710017
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21.2 Package Details
The following sections give the technical details of the packages.
28-Lead Skinny Plastic Dual In-Line (SP) - 300 mil Body [SPDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
N NOTE 1 E1
1
2
3 D E
A
A2 L c eB
A1
b1 b e
Units Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing N e A A2 A1 E E1 D L c b1 b eB - .120 .015 .290 .240 1.345 .110 .008 .040 .014 - MIN
INCHES NOM 28 .100 BSC - .135 - .310 .285 1.365 .130 .010 .050 .018 - .200 .150 - .335 .295 1.400 .150 .015 .070 .022 MAX
.430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-070B
(c) 2007 Microchip Technology Inc.
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40-Lead Plastic Dual In-Line (P) - 600 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
N NOTE 1 E1
123 D
E A A2 L A1 b1 b e
Units Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing N e A A2 A1 E E1 D L c b1 b eB - .125 .015 .590 .485 1.980 .115 .008 .030 .014 - MIN INCHES NOM 40 .100 BSC - - - - - - - - - - - .250 .195 - .625 .580 2.095 .200 .015 .070 .023 MAX
c eB
.700 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-016B
DS41250F-page 308
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PIC16F913/914/916/917/946
28-Lead Plastic Quad Flat, No Lead Package (ML) - 6x6 mm Body [QFN] with 0.55 mm Contact Length
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D D2
EXPOSED PAD
e E E2 2 1 N NOTE 1 TOP VIEW BOTTOM VIEW 2 1 N L K
b
A
A3
A1
Units Dimension Limits Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Width Exposed Pad Width Overall Length Exposed Pad Length Contact Width Contact Length Contact-to-Exposed Pad N e A A1 A3 E E2 D D2 b L K 3.65 0.23 0.50 0.20 3.65 0.80 0.00 MIN MILLIMETERS NOM 28 0.65 BSC 0.90 0.02 0.20 REF 6.00 BSC 3.70 6.00 BSC 3.70 0.30 0.55 - 4.20 0.35 0.70 - 4.20 1.00 0.05 MAX
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-105B
(c) 2007 Microchip Technology Inc.
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44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D D2
EXPOSED PAD
e E E2 b 2 1 N TOP VIEW NOTE 1 2 1 N L BOTTOM VIEW K
A A3 A1
Units Dimension Limits Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Width Exposed Pad Width Overall Length Exposed Pad Length Contact Width Contact Length Contact-to-Exposed Pad N e A A1 A3 E E2 D D2 b L K 6.30 0.25 0.30 0.20 6.30 0.80 0.00 MIN MILLIMETERS NOM 44 0.65 BSC 0.90 0.02 0.20 REF 8.00 BSC 6.45 8.00 BSC 6.45 0.30 0.40 - 6.80 0.38 0.50 - 6.80 1.00 0.05 MAX
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-103B
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PIC16F913/914/916/917/946
28-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N
E E1 NOTE 1 123 b e

h h c
A
A2
L A1 L1
Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer (optional) Foot Length Footprint Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 E E1 D h L L1 c b 0 0.18 0.31 5 5 0.25 0.40 - 2.05 0.10 MIN
MILLIMETERS NOM 28 1.27 BSC - - - 10.30 BSC 7.50 BSC 17.90 BSC - - 1.40 REF - - - - - 8 0.33 0.51 15 0.75 1.27 2.65 - 0.30 MAX
15 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-052B
(c) 2007 Microchip Technology Inc.
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PIC16F913/914/916/917/946
28-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N
E E1
12 NOTE 1
b e
c A A2 L1
Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Footprint Lead Thickness Foot Angle Lead Width N e A A2 A1 E E1 D L L1 c b 0.09 0 0.22 - 1.65 0.05 7.40 5.00 9.90 0.55 MIN MILLIMETERS NOM 28 0.65 BSC - 1.75 - 7.80 5.30 10.20 0.75 1.25 REF - 4 - 0.25 8 0.38 2.00 1.85 - 8.20 5.60 10.50 0.95 MAX
A1
L
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-073B
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44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D D1
E e E1
b
N 123
NOTE 1 c
NOTE 2 A
L
A1
L1
A2
Units Dimension Limits Number of Leads Lead Pitch Overall Height Molded Package Thickness Standoff Foot Length Footprint Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 L L1 E D E1 D1 c b 0.09 0.30 11 11 0 - 0.95 0.05 0.45 MIN
MILLIMETERS NOM 44 0.80 BSC - 1.00 - 0.60 1.00 REF 3.5 12.00 BSC 12.00 BSC 10.00 BSC 10.00 BSC - 0.37 12 12 0.20 0.45 13 13 7 1.20 1.05 0.15 0.75 MAX
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-076B
(c) 2007 Microchip Technology Inc.
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64-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D D1
E e E1
N b NOTE 1 123 NOTE 2 A c A2
L
A1
L1
Units Dimension Limits Number of Leads Lead Pitch Overall Height Molded Package Thickness Standoff Foot Length Footprint Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 L L1 E D E1 D1 c b 0.09 0.17 11 11 0 - 0.95 0.05 0.45 MIN
MILLIMETERS NOM 64 0.50 BSC - 1.00 - 0.60 1.00 REF 3.5 12.00 BSC 12.00 BSC 10.00 BSC 10.00 BSC - 0.22 12 12 0.20 0.27 13 13 7 1.20 1.05 0.15 0.75 MAX
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-085B
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APPENDIX A:
Revision A
This is a new data sheet.
DATA SHEET REVISION HISTORY
APPENDIX B:
MIGRATING FROM OTHER PIC(R) DEVICES
This discusses some of the issues in migrating from other PIC(R) devices to the PIC16F91X/946 family of devices.
Revision B
Updated Peripheral Features. Page 2, Table: Corrected I/O numbers. Figure 8-3: Revised Comparator I/O operating modes. Register 9-1, Table: Corrected max. number of pixels.
B.1
PIC16F676 to PIC16F91X/946
FEATURE COMPARISON
PIC16F676 20 MHz 1K 64 10-bit 128 1/1 8 Y RB0/1/2/4/5 RB0/1/2/3 /4/5 1 N N N 4 MHz N PIC16F91X/ 946 20 MHz 8K 352 10-bit 256 2/1 8 Y RB<7:0> RB<7:4> 2 Y Y Y 32 kHz 8 MHz Y
TABLE B-1:
Feature
Revision C
Correction to Pin Description Table. Correction to IPD base and T1OSC.
Max. Operating Speed Max. Program Memory (Words) Max. SRAM (Bytes) A/D Resolution Data EEPROM (bytes) Timers (8/16-bit) Oscillator Modes Brown-out Reset Internal Pull-ups Interrupt-on-change Comparator USART Extended WDT Software Control Option of WDT/BOR INTOSC Frequencies Clock Switching
Revision D
Revised references 31.25 kHz to 31 kHz. Revised Standby Current to 100 nA. Revised 9.1: internal RC oscillator to internal LF oscillator.
Revision E
Removed "Advance Information" from Section 19.0 Electrical Specifications. Removed 28-Lead Plastic Quad Flat No Lead Package (ML) (QFN-S) package.
Revision F
Updates throughout document. Removed "Preliminary" from Data Sheet. Added Characterization Data chapter. Update Electrical Specifications chapter. Added PIC16F946 device.
(c) 2007 Microchip Technology Inc.
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APPENDIX C: CONVERSION CONSIDERATIONS
Considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in Table C-1.
TABLE C-1:
Pins Timers Interrupts Communication Frequency Voltage A/D CCP Comparator
CONVERSION CONSIDERATIONS
PIC16F91X/946 28/40/64 3 11 or 12 USART, SSP(1) (SPI, I2CTM Slave) 20 MHz 2.0V-5.5V 10-bit, 7 conversion clock selects 2 2 Yes 4K, 8K Flash PIC16F87X 28/40 3 13 or 14 PSP, USART, SSP (SPI, I2C Master/Slave) 20 MHz 2.2V-5.5V 10-bit, 4 conversion clock selects 2 -- -- 4K, 8K Flash (Erase/Write on single-word) 192, 368 bytes 128, 256 bytes Segmented, starting at end of program memory On/Off PIC16F87XA 28/40 3 14 or 15 PSP, USART, SSP (SPI, I2C Master/Slave) 20 MHz 2.0V-5.5V 10-bit, 7 conversion clock selects 2 2 Yes 4K, 8K Flash (Erase/Write on four-word blocks) 192, 368 bytes 128, 256 bytes On/Off Segmented, starting at beginning of program memory -- In-Circuit Debugger, Low-Voltage Programming
Characteristic
Comparator Voltage Reference Program Memory
RAM EEPROM Data Code Protection Program Memory Write Protection LCD Module Other Note 1:
256, 336, 352 bytes 256 bytes On/Off --
16, 24 segment drivers, 4 commons In-Circuit Debugger, Low-Voltage Programming
-- In-Circuit Debugger, Low-Voltage Programming
SSP aand USART share the same pins on the PIC16F91X.
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INDEX
A
A/D Specifications.................................................... 272, 273 Absolute Maximum Ratings .............................................. 255 AC Characteristics Industrial and Extended ............................................ 265 Load Conditions ........................................................ 264 ACK pulse ......................................................................... 202 ADC .................................................................................. 175 Acquisition Requirements ......................................... 183 Associated registers.................................................. 185 Block Diagram........................................................... 175 Calculating Acquisition Time..................................... 183 Channel Selection..................................................... 176 Configuration............................................................. 176 Configuring Interrupt ................................................. 179 Conversion Clock...................................................... 176 Conversion Procedure .............................................. 179 Internal Sampling Switch (RSS) Impedance.............. 183 Interrupts................................................................... 177 Operation .................................................................. 178 Operation During Sleep ............................................ 178 Port Configuration ..................................................... 176 Reference Voltage (VREF)......................................... 176 Result Formatting...................................................... 178 Source Impedance.................................................... 183 Special Event Trigger................................................ 178 Starting an A/D Conversion ...................................... 178 ADCON0 Register............................................................. 180 ADCON1 Register............................................................. 181 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART)....... 121 ADRESH Register (ADFM = 0) ......................................... 182 ADRESH Register (ADFM = 1) ......................................... 182 ADRESL Register (ADFM = 0).......................................... 182 ADRESL Register (ADFM = 1).......................................... 182 Analog Input Connection Considerations.......................... 111 Analog-to-Digital Converter. See ADC ANSEL Register .................................................................. 43 Assembler MPASM Assembler................................................... 252 AUSART ........................................................................... 121 Associated Registers Baud Rate Generator........................................ 132 Asynchronous Mode ................................................. 123 Associated Registers Receive..................................................... 129 Transmit.................................................... 125 Baud Rate Generator (BRG) ............................ 132 Receiver............................................................ 126 Setting up 9-bit Mode with Address Detect....... 128 Transmitter........................................................ 123 Baud Rate Generator (BRG) Baud Rate Error, Calculating ............................ 132 Baud Rates, Asynchronous Modes .................. 133 Formulas ........................................................... 132 High Baud Rate Select (BRGH Bit) .................. 132 Synchronous Master Mode ............................... 135, 139 Associated Registers Receive..................................................... 138 Transmit.................................................... 136 Reception.......................................................... 137 Transmission .................................................... 135 Synchronous Slave Mode (c) 2007 Microchip Technology Inc. Associated Registers Receive .................................................... 140 Transmit ................................................... 139 Reception ......................................................... 140 Transmission .................................................... 139
B
BF bit ................................................................................ 194 Block Diagram of RF........................................................... 83 Block Diagrams (CCP) Capture Mode Operation ............................... 213 ADC .......................................................................... 175 ADC Transfer Function............................................. 184 Analog Input Model........................................... 111, 184 AUSART Receive ..................................................... 122 AUSART Transmit .................................................... 121 CCP PWM ................................................................ 215 Clock Source .............................................................. 87 Comparator 1............................................................ 110 Comparator 2............................................................ 110 Comparator Modes................................................... 113 Compare................................................................... 214 Crystal Operation........................................................ 90 External RC Mode ...................................................... 91 Fail-Safe Clock Monitor (FSCM)................................. 97 In-Circuit Serial Programming Connections ............. 238 Interrupt Logic........................................................... 231 LCD Clock Generation.............................................. 150 LCD Driver Module ................................................... 144 LCD Resistor Ladder Connection............................. 148 MCLR Circuit ............................................................ 222 On-Chip Reset Circuit............................................... 221 PIC16F913/916 .......................................................... 15 PIC16F914/917 .......................................................... 16 PIC16F946 ................................................................. 17 RA0 Pin ...................................................................... 45 RA1 Pin ...................................................................... 46 RA2 Pin ...................................................................... 47 RA3 Pin ...................................................................... 48 RA4 Pin ...................................................................... 49 RA5 Pin ...................................................................... 50 RA6 Pin ...................................................................... 51 RA7 Pin ...................................................................... 52 RB Pins....................................................................... 56 RB4 Pin ...................................................................... 57 RB5 Pin ...................................................................... 58 RB6 Pin ...................................................................... 59 RB7 Pin ...................................................................... 60 RC0 Pin ...................................................................... 63 RC1 Pin ...................................................................... 64 RC2 Pin ...................................................................... 64 RC3 Pin ...................................................................... 65 RC4 Pin ...................................................................... 66 RC5 Pin ...................................................................... 67 RC6 Pin ...................................................................... 68 RC7 Pin ...................................................................... 69 RD Pins ...................................................................... 74 RD0 Pin ...................................................................... 73 RD1 Pin ...................................................................... 73 RD2 Pin ...................................................................... 74 RE Pins....................................................................... 78 RE Pins....................................................................... 79 Resonator Operation .................................................. 90 RF Pins....................................................................... 83
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PIC16F917/916/914/913
RG Pins....................................................................... 85 SSP (I2C Mode) ........................................................ 202 SSP (SPI Mode)........................................................ 193 Timer1 ....................................................................... 102 Timer2 ....................................................................... 107 TMR0/WDT Prescaler ................................................. 99 Watchdog Timer (WDT) ............................................ 234 Brown-out Reset (BOR) .................................................... 223 Associated Registers ................................................ 224 Calibration ................................................................. 223 Specifications ............................................................ 269 Timing and Characteristics ....................................... 268 Assigning Prescaler to WDT..................................... 100 Call of a Subroutine in Page 1 from Page 0 ............... 40 Changing Between Capture Prescalers.................... 213 Indirect Addressing ..................................................... 41 Initializing PORTA....................................................... 44 Initializing PORTB....................................................... 53 Initializing PORTC ...................................................... 62 Initializing PORTD ...................................................... 71 Initializing PORTE....................................................... 76 Initializing PORTF....................................................... 81 Initializing PORTG ...................................................... 84 Loading the SSPBUF (SSPSR) Register.................. 196 Saving Status and W Registers in RAM ................... 233 Code Protection ................................................................ 238 Comparator....................................................................... 109 C2OUT as T1 Gate................................................... 117 Configurations .......................................................... 112 Interrupts .................................................................. 114 Operation .......................................................... 109, 114 Operation During Sleep ............................................ 115 Response Time......................................................... 114 Synchronizing COUT w/Timer1 ................................ 117 Comparator Module Associated registers ................................................. 119 Comparator Voltage Reference (CVREF) Response Time......................................................... 114 Comparator Voltage Reference (CVREF) .......................... 118 Effects of a Reset ..................................................... 115 Specifications ........................................................... 271 Comparators C2OUT as T1 Gate................................................... 103 Effects of a Reset ..................................................... 115 Specifications ........................................................... 271 Compare Module. See Capture/Compare/PWM (CCP) CONFIG1 Register ........................................................... 220 Configuration Bits ............................................................. 220 Conversion Considerations............................................... 316 CPU Features ................................................................... 219 Customer Change Notification Service............................. 325 Customer Notification Service .......................................... 325 Customer Support............................................................. 325
C
C Compilers MPLAB C18 .............................................................. 252 MPLAB C30 .............................................................. 252 Capture Module. See Capture/Compare/PWM (CCP) Capture/Compare/PWM (CCP)......................................... 211 Associated registers w/ Capture/Compare/PWM...... 218 Capture Mode ........................................................... 213 CCPx Pin Configuration ............................................ 213 Compare Mode ......................................................... 214 CCPx Pin Configuration .................................... 214 Software Interrupt Mode ........................... 213, 214 Special Event Trigger........................................ 214 Timer1 Mode Selection ............................. 213, 214 Interaction of Two CCP Modules (table) ................... 211 Prescaler ................................................................... 213 PWM Mode ............................................................... 215 Duty Cycle......................................................... 216 Effects of Reset................................................. 218 Example PWM Frequencies and Resolutions, 20 MHZ ................................ 217 Example PWM Frequencies and Resolutions, 8 MHz................................... 217 Operation in Sleep Mode .................................. 218 Setup for Operation........................................... 218 System Clock Frequency Changes................... 218 PWM Period .............................................................. 216 Setup for PWM Operation ......................................... 218 Timer Resources....................................................... 211 CCP. See Capture/Compare/PWM (CCP) CCPxCON Register .......................................................... 212 CKE bit .............................................................................. 194 CKP bit .............................................................................. 195 Clock Sources External Modes ........................................................... 89 EC ....................................................................... 89 HS ....................................................................... 90 LP........................................................................ 90 OST..................................................................... 89 RC....................................................................... 91 XT ....................................................................... 90 Internal Modes ............................................................ 91 Frequency Selection ........................................... 93 HFINTOSC.......................................................... 91 INTOSC .............................................................. 91 INTOSCIO........................................................... 91 LFINTOSC .......................................................... 93 Clock Switching................................................................... 95 CMCON0 Register ............................................................ 116 CMCON1 Register ............................................................ 117 Code Examples A/D Conversion ......................................................... 179 Assigning Prescaler to Timer0 .................................. 100
D
D/A bit ............................................................................... 194 Data EEPROM Memory.................................................... 187 Associated Registers ................................................ 192 Reading .................................................................... 190 Writing ...................................................................... 190 Data Memory ...................................................................... 24 Data/Address bit (D/A)...................................................... 194 DC and AC Characteristics Graphs and Tables ................................................... 283 DC Characteristics Extended and Industrial ............................................ 261 Industrial and Extended ............................................ 257 Development Support ....................................................... 251 Device Overview................................................................. 15
E
EEADRH Registers................................................... 187, 188 EEADRL Register ............................................................. 188 EEADRL Registers ........................................................... 187 EECON1 Register..................................................... 187, 189 EECON2 Register............................................................. 187 EEDATH Register............................................................. 188 EEDATL Register ............................................................. 188
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Effects of Reset PWM mode ............................................................... 218 Electrical Specifications .................................................... 255 Errata .................................................................................. 13 SLEEP ...................................................................... 248 SUBLW..................................................................... 248 SUBWF..................................................................... 249 SWAPF..................................................................... 249 XORLW .................................................................... 249 XORWF .................................................................... 249 Summary Table ........................................................ 242 INTCON Register................................................................ 34 Inter-Integrated Circuit (I2C). See I2C Mode Internal Oscillator Block INTOSC Specifications ........................................... 266, 267 Internal Sampling Switch (RSS) Impedance ..................... 183 Internet Address ............................................................... 325 Interrupts .......................................................................... 230 ADC .......................................................................... 179 Associated Registers................................................ 232 Comparator............................................................... 114 Context Saving ......................................................... 233 Interrupt-on-change .................................................... 53 PORTB Interrupt-on-Change.................................... 231 RB0/INT/SEG0 ......................................................... 231 TMR0........................................................................ 231 TMR1........................................................................ 104 INTOSC Specifications ............................................. 266, 267 IOCB Register..................................................................... 54
F
Fail-Safe Clock Monitor....................................................... 97 Fail-Safe Condition Clearing ....................................... 97 Fail-Safe Detection ..................................................... 97 Fail-Safe Operation..................................................... 97 Reset or Wake-up from Sleep..................................... 97 Firmware Instructions........................................................ 241 Flash Program Memory .................................................... 187 Fuses. See Configuration Bits
G
General Purpose Register File............................................ 24
I
I/O Ports .............................................................................. 43 I2C Mode Addressing ................................................................ 203 Associated Registers ................................................ 209 Master Mode ............................................................. 208 Mode Selection ......................................................... 202 Multi-Master Mode .................................................... 208 Operation .................................................................. 202 Reception.................................................................. 204 Slave Mode SCL and SDA pins ............................................ 202 Transmission............................................................. 206 ID Locations ...................................................................... 238 In-Circuit Debugger ........................................................... 239 In-Circuit Serial Programming (ICSP) ............................... 238 Indirect Addressing, INDF and FSR Registers ................... 41 Instruction Format ............................................................. 241 Instruction Set ................................................................... 241 ADDLW ..................................................................... 243 ADDWF..................................................................... 243 ANDLW ..................................................................... 243 ANDWF..................................................................... 243 BCF........................................................................... 243 BSF ........................................................................... 243 BTFSC ...................................................................... 243 BTFSS ...................................................................... 244 CALL ......................................................................... 244 CLRF......................................................................... 244 CLRW ....................................................................... 244 CLRWDT................................................................... 244 COMF ....................................................................... 244 DECF ........................................................................ 244 DECFSZ.................................................................... 245 GOTO ....................................................................... 245 INCF.......................................................................... 245 INCFSZ ..................................................................... 245 IORLW ...................................................................... 245 IORWF ...................................................................... 245 MOVF........................................................................ 246 MOVLW .................................................................... 246 MOVWF .................................................................... 246 NOP .......................................................................... 246 RETFIE ..................................................................... 247 RETLW ..................................................................... 247 RETURN ................................................................... 247 RLF ........................................................................... 248 RRF........................................................................... 248
L
LCD Associated Registers................................................ 168 Bias Types................................................................ 148 Clock Source Selection ............................................ 148 Configuring the Module ............................................ 167 Disabling the Module ................................................ 167 Frame Frequency ..................................................... 149 Interrupts .................................................................. 164 LCDCON Register .................................................... 143 LCDDATA Register .................................................. 143 LCDPS Register ....................................................... 143 Multiplex Types......................................................... 149 Operation During Sleep ............................................ 165 Pixel Control ............................................................. 149 Prescaler .................................................................. 148 Segment Enables ..................................................... 149 Waveform Generation .............................................. 153 LCDCON Register .................................................... 143, 145 LCDDATA Register........................................................... 143 LCDDATAx Registers ....................................................... 147 LCDPS Register ....................................................... 143, 146 LP Bits ...................................................................... 148 LCDSEn Registers............................................................ 147 Liquid Crystal Display (LCD) Driver .................................. 143 Load Conditions................................................................ 264
M
MCLR ............................................................................... 222 Internal...................................................................... 222 Memory Organization ......................................................... 23 Data ............................................................................ 24 Program...................................................................... 23 Microchip Internet Web Site.............................................. 325 Migrating from other PIC Microcontroller Devices ............ 315 MPLAB ASM30 Assembler, Linker, Librarian ................... 252 MPLAB ICD 2 In-Circuit Debugger ................................... 253 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator.................................................... 253
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MPLAB Integrated Development Environment Software .. 251 MPLAB PM3 Device Programmer..................................... 253 MPLAB REAL ICE In-Circuit Emulator System................. 253 MPLINK Object Linker/MPLIB Object Librarian ................ 252 RA6............................................................................. 51 RA7............................................................................. 52 Registers .................................................................... 44 Specifications ........................................................... 267 PORTA Register ................................................................. 44 PORTB Additional Pin Functions ............................................. 53 Weak Pull-up ...................................................... 53 Associated Registers .................................................. 61 Interrupt-on-change .................................................... 53 Pin Descriptions and Diagrams .................................. 56 RB0............................................................................. 56 RB1............................................................................. 56 RB2............................................................................. 56 RB3............................................................................. 56 RB4............................................................................. 57 RB5............................................................................. 58 RB6............................................................................. 59 RB7............................................................................. 60 Registers .................................................................... 53 PORTB Register ................................................................. 54 PORTC Associated Registers .................................................. 70 Pin Descriptions and Diagrams .................................. 63 RC0 ............................................................................ 63 RC1 ............................................................................ 63 RC2 ............................................................................ 63 RC3 ............................................................................ 65 RC4 ............................................................................ 66 RC5 ............................................................................ 67 RC6 ............................................................................ 68 RC7 ............................................................................ 69 Registers .................................................................... 62 Specifications ........................................................... 267 PORTC Register................................................................. 62 PORTD Associated Registers .................................................. 75 Pin Descriptions and Diagrams .................................. 72 RD0 ............................................................................ 72 RD1 ............................................................................ 72 RD2 ............................................................................ 72 RD3 ............................................................................ 72 RD4 ............................................................................ 72 RD5 ............................................................................ 72 RD6 ............................................................................ 72 RD7 ............................................................................ 72 Registers .................................................................... 71 PORTD Register................................................................. 71 PORTE Associated Registers .................................................. 80 Pin Descriptions and Diagrams .................................. 77 RE0............................................................................. 77 RE1............................................................................. 77 RE2............................................................................. 77 RE3............................................................................. 77 RE4............................................................................. 77 RE5............................................................................. 77 RE6............................................................................. 77 RE7............................................................................. 77 Registers .................................................................... 76 PORTE Register ................................................................. 76 PORTF Associated Registers .................................................. 83 Pin Descriptions and Diagrams .................................. 82 Registers .................................................................... 81
O
OPCODE Field Descriptions ............................................. 241 OPTION Register ................................................................ 33 OPTION_REG Register .................................................... 101 OSCCON Register .............................................................. 88 Oscillator Associated registers............................................ 98, 106 Oscillator Module ................................................................ 87 EC ............................................................................... 87 HFINTOSC.................................................................. 87 HS ............................................................................... 87 INTOSC ...................................................................... 87 INTOSCIO................................................................... 87 LFINTOSC .................................................................. 87 LP................................................................................ 87 RC ............................................................................... 87 RCIO ........................................................................... 87 XT ............................................................................... 87 Oscillator Parameters........................................................ 266 Oscillator Specifications .................................................... 265 Oscillator Start-up Timer (OST) Specifications ............................................................ 269 Oscillator Switching Fail-Safe Clock Monitor............................................... 97 Two-Speed Clock Start-up .......................................... 95 OSCTUNE Register ............................................................ 92
P
P (Stop) bit ........................................................................ 194 Packaging ......................................................................... 305 Marking ............................................................. 305, 306 PDIP Details.............................................................. 307 Paging, Program Memory ................................................... 40 PCL and PCLATH ............................................................... 40 Computed GOTO ........................................................ 40 Stack ........................................................................... 40 PCON Register ........................................................... 39, 224 PICSTART Plus Development Programmer ..................... 254 PIE1 Register ...................................................................... 35 PIE2 Register ...................................................................... 36 Pin Diagram PIC16F913/916, 28-pin ................................................. 4 PIC16F914/917, 40-pin ................................................. 2 PIC16F914/917, 44-pin ................................................. 7 PIC16F946, 64-Pin ..................................................... 10 Pinout Description ............................................................... 18 PIR1 Register...................................................................... 37 PIR2 Register...................................................................... 38 PLVD Associated Registers ................................................ 173 PORTA Additional Pin Functions ANSEL Register.................................................. 43 Associated Registers .................................................. 52 Pin Descriptions and Diagrams................................... 45 RA0 ............................................................................. 45 RA1 ............................................................................. 46 RA2 ............................................................................. 47 RA3 ............................................................................. 48 RA4 ............................................................................. 49 RA5 ............................................................................. 50
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PIC16F917/916/914/913
RF0 ............................................................................. 82 RF1 ............................................................................. 82 RF2 ............................................................................. 82 RF3 ............................................................................. 82 RF4 ............................................................................. 82 RF5 ............................................................................. 82 RF6 ............................................................................. 82 RF7 ............................................................................. 82 PORTF Register ................................................................. 81 PORTG Associated Registers .................................................. 86 Pin Descriptions and Diagrams................................... 85 Registers..................................................................... 84 RG0............................................................................. 85 RG1............................................................................. 85 RG2............................................................................. 85 RG3............................................................................. 85 RG4............................................................................. 85 RG5............................................................................. 85 PORTG Register ................................................................. 84 Power-Down Mode (Sleep) ............................................... 236 Power-on Reset ................................................................ 222 Power-up Timer (PWRT) .................................................. 222 Specifications............................................................ 269 Precision Internal Oscillator Parameters........................... 267 Prescaler Shared WDT/Timer0 ................................................. 100 Switching Prescaler Assignment............................... 100 Product Identification System ........................................... 327 Program Memory ................................................................ 23 Map and Stack (PIC16F913/914) ............................... 23 Map and Stack (PIC16F916/917/946) ........................ 23 Paging......................................................................... 40 Programmable Low-Voltage Detect (PLVD) Module ........ 171 PLVD Operation........................................................ 171 Programming, Device Instructions .................................... 241 LCDSEn (LCD Segment Enable) ............................. 147 LVDCON (Low-Voltage Detect Control) ................... 173 OPTION_REG (OPTION)................................... 33, 101 OSCCON (Oscillator Control)..................................... 88 OSCTUNE (Oscillator Tuning).................................... 92 PCON (Power Control Register)................................. 39 PCON (Power Control) ............................................. 224 PIE1 (Peripheral Interrupt Enable 1) .......................... 35 PIE2 (Peripheral Interrupt Enable 2) .......................... 36 PIR1 (Peripheral Interrupt Register 1) ........................ 37 PIR2 (Peripheral Interrupt Request 2) ........................ 38 PORTA ....................................................................... 44 PORTB ....................................................................... 54 PORTC ....................................................................... 62 PORTD ....................................................................... 71 PORTE ....................................................................... 76 PORTF ....................................................................... 81 PORTG....................................................................... 84 RCSTA (Receive Status and Control) ...................... 131 Reset Values ............................................................ 226 Reset Values (Special Registers)............................. 229 Special Function Register Map PIC16F913/916 .................................................. 25 PIC16F914/917 .................................................. 26 PIC16F946 ......................................................... 27 Special Register Summary Bank 0 ................................................................ 28 Bank 1 ................................................................ 29 Bank 2 ................................................................ 30 Bank 3 ................................................................ 31 SSPCON (Sync Serial Port Control) Register .......... 195 SSPSTAT (Sync Serial Port Status) Register .......... 194 STATUS ..................................................................... 32 T1CON ..................................................................... 105 T2CON ..................................................................... 108 TRISA (Tri-State PORTA) .......................................... 44 TRISB (Tri-State PORTB) .......................................... 54 TRISC (Tri-State PORTC) .......................................... 62 TRISD (Tri-State PORTD) .......................................... 71 TRISE (Tri-State PORTE) .......................................... 76 TRISF (Tri-State PORTF)........................................... 81 TRISG (Tri-State PORTG).......................................... 84 TXSTA (Transmit Status and Control)...................... 130 VRCON (Voltage Reference Control) ....................... 118 WDTCON (Watchdog Timer Control) ....................... 235 WPUB (Weak Pull-up PORTB)................................... 55 Reset ................................................................................ 221 Revision History................................................................ 315
R
R/W bit .............................................................................. 194 RCREG ............................................................................. 128 RCSTA Register ............................................................... 131 Reader Response ............................................................. 326 Read-Modify-Write Operations ......................................... 241 Receive Overflow Indicator bit (SSPOV) .......................... 195 Registers ADCON0 (ADC Control 0) ........................................ 180 ADCON1 (ADC Control 1) ........................................ 181 ADRESH (ADC Result High) with ADFM = 0)........... 182 ADRESH (ADC Result High) with ADFM = 1)........... 182 ADRESL (ADC Result Low) with ADFM = 0) ............ 182 ADRESL (ADC Result Low) with ADFM = 1) ............ 182 ANSEL (Analog Select)............................................... 43 CCPxCON (CCP Operation)..................................... 212 CMCON0 (Comparator Control 0) ............................ 116 CMCON1 (Comparator Control 1) ............................ 117 CONFIG1 (Configuration Word Register 1) .............. 220 EEADRH (EEPROM Address High Byte) ................. 188 EEADRL (EEPROM Address Low Byte)................... 188 EECON1 (EEPROM Control 1)................................. 189 EEDATH (EEPROM Data High Byte) ....................... 188 EEDATL (EEPROM Data Low Byte)......................... 188 INTCON (Interrupt Control)......................................... 34 IOCB (PORTB Interrupt-on-change)........................... 54 LCDCON (LCD Control)............................................ 145 LCDDATAx (LCD Data) ............................................ 147 LCDPS (LCD Prescaler Select) ................................ 146
S
S (Start) bit ....................................................................... 194 Slave Select Synchronization ........................................... 199 SMP bit ............................................................................. 194 Software Simulator (MPLAB SIM) .................................... 252 SPBRG ............................................................................. 132 Special Event Trigger ....................................................... 178 Special Function Registers ................................................. 24 SPI Mode .................................................................. 193, 199 Associated Registers................................................ 201 Bus Mode Compatibility ............................................ 201 Effects of a Reset ..................................................... 201 Enabling SPI I/O ....................................................... 197 Master Mode............................................................. 198 Master/Slave Connection ......................................... 197 Serial Clock (SCK pin) .............................................. 193 Serial Data In (SDI pin)............................................. 193
(c) 2007 Microchip Technology Inc.
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Serial Data Out (SDO pin) ........................................ 193 Slave Select .............................................................. 193 Slave Select Synchronization ................................... 199 Sleep Operation ........................................................ 201 SPI Clock .................................................................. 198 Typical Connection ................................................... 197 SSP Overview SPI Master/Slave Connection ................................... 197 SSP I2C Operation ............................................................ 202 Slave Mode ............................................................... 202 SSP Module Clock Synchronization and the CKP Bit .................... 208 SPI Master Mode ...................................................... 198 SPI Slave Mode ........................................................ 199 SSPBUF.................................................................... 198 SSPSR ...................................................................... 198 SSPCON Register............................................................. 195 SSPEN bit ......................................................................... 195 SSPM bits ......................................................................... 195 SSPOV bit ......................................................................... 195 SSPSTAT Register ........................................................... 194 STATUS Register................................................................ 32 Synchronous Serial Port Enable bit (SSPEN)................... 195 Synchronous Serial Port Mode Select bits (SSPM) .......... 195 Synchronous Serial Port. See SSP Asynchronous Transmission..................................... 124 Asynchronous Transmission (Back-to-Back)............ 124 Brown-out Reset (BOR)............................................ 268 Brown-out Reset Situations ...................................... 223 Capture/Compare/PWM ........................................... 276 CLKOUT and I/O ...................................................... 267 Clock Synchronization .............................................. 209 Clock Timing ............................................................. 265 Comparator Output ................................................... 109 Fail-Safe Clock Monitor (FSCM)................................. 98 I2C Bus Data............................................................. 281 I2C Bus Start/Stop Bits ............................................. 280 I2C Reception (7-bit Address)................................... 204 I2C Slave Mode (Transmission, 10-bit Address)....... 207 I2C Slave Mode with SEN = 0 (Reception, 10-bit Address) ................................................. 205 I2C Transmission (7-bit Address).............................. 206 INT Pin Interrupt ....................................................... 232 Internal Oscillator Switch Timing ................................ 94 LCD Interrupt Timing in Quarter-Duty Cycle Drive ... 164 LCD Sleep Entry/Exit when SLPEN = 1 or CS = 00 . 166 Reset, WDT, OST and Power-up Timer ................... 268 Slave Synchronization .............................................. 199 SPI Master Mode (CKE = 1, SMP = 1) ..................... 278 SPI Mode (Master Mode).......................................... 198 SPI Mode (Slave Mode with CKE = 0)...................... 200 SPI Mode (Slave Mode with CKE = 1)...................... 200 SPI Slave Mode (CKE = 0) ....................................... 279 SPI Slave Mode (CKE = 1) ....................................... 279 Synchronous Reception (Master Mode, SREN) ....... 138 Synchronous Transmission ...................................... 136 Synchronous Transmission (Through TXEN) ........... 136 Time-out Sequence Case 1 .............................................................. 225 Case 2 .............................................................. 225 Case 3 .............................................................. 225 Timer0 and Timer1 External Clock ........................... 270 Timer1 Incrementing Edge ....................................... 104 Two Speed Start-up.................................................... 96 Type-A in 1/2 Mux, 1/2 Bias Drive ............................ 154 Type-A in 1/2 Mux, 1/3 Bias Drive ............................ 156 Type-A in 1/3 Mux, 1/2 Bias Drive ............................ 158 Type-A in 1/3 Mux, 1/3 Bias Drive ............................ 160 Type-A in 1/4 Mux, 1/3 Bias Drive ............................ 162 Type-A/Type-B in Static Drive .................................. 153 Type-B in 1/2 Mux, 1/2 Bias Drive ............................ 155 Type-B in 1/2 Mux, 1/3 Bias Drive ............................ 157 Type-B in 1/3 Mux, 1/2 Bias Drive ............................ 159 Type-B in 1/3 Mux, 1/3 Bias Drive ............................ 161 Type-B in 1/4 Mux, 1/3 Bias Drive ............................ 163 USART Synchronous Receive (Master/Slave) ......... 275 USART Synchronous Transmission (Master/Slave). 275 Wake-up from Interrupt............................................. 237 Timing Parameter Symbology .......................................... 264 Timing Requirements I2C Bus Data............................................................. 282 I2C Bus Start/Stop Bits ............................................. 281 SPI Mode .................................................................. 280 TRISA Registers .................................................................... 44 TRISA Register................................................................... 44 TRISB Registers .................................................................... 53 TRISB Register................................................................... 54 TRISC
T
T1CON Register................................................................ 105 T2CON Register................................................................ 108 Thermal Considerations .................................................... 263 Time-out Sequence........................................................... 224 Timer0 ................................................................................. 99 Associated Registers ................................................ 101 External Clock ........................................................... 100 Interrupt..................................................................... 101 Operation ............................................................ 99, 102 Specifications ............................................................ 270 T0CKI ........................................................................ 100 Timer1 ............................................................................... 102 Associated registers.................................................. 106 Asynchronous Counter Mode ................................... 103 Reading and Writing ......................................... 103 Interrupt..................................................................... 104 Modes of Operation .................................................. 102 Operation During Sleep ............................................ 104 Oscillator ................................................................... 103 Prescaler ................................................................... 103 Specifications ............................................................ 270 Timer1 Gate Inverting Gate ................................................... 103 Selecting Source....................................... 103, 117 Synchronizing COUT w/Timer1 ........................ 117 TMR1H Register ....................................................... 102 TMR1L Register ........................................................ 102 Timer2 Associated registers.................................................. 108 Timers Timer1 T1CON.............................................................. 105 Timer2 T2CON.............................................................. 108 Timing Diagrams A/D Conversion ......................................................... 274 A/D Conversion (Sleep Mode) .................................. 274 Asynchronous Reception .......................................... 128
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(c) 2007 Microchip Technology Inc.
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Registers..................................................................... 62 TRISC Register ................................................................... 62 TRISD Registers..................................................................... 71 TRISD Register ................................................................... 71 TRISE Registers..................................................................... 76 TRISE Register ................................................................... 76 TRISF Registers..................................................................... 81 TRISF Register ................................................................... 81 TRISG Registers..................................................................... 84 TRISG Register................................................................... 84 Two-Speed Clock Start-up Mode ........................................ 95 TXREG.............................................................................. 123 TXSTA Register ................................................................ 130 BRGH Bit .................................................................. 132
U
UA ..................................................................................... 194 Update Address bit, UA .................................................... 194 USART Synchronous Master Mode Requirements, Synchronous Receive .............. 275 Requirements, Synchronous Transmission ...... 275 Timing Diagram, Synchronous Receive ........... 275 Timing Diagram, Synchronous Transmission ... 275
V
Voltage Reference. See Comparator Voltage Reference (CVREF) Voltage References Associated registers.................................................. 119 VREF. SEE ADC Reference Voltage
W
Wake-up Using Interrupts ................................................. 236 Watchdog Timer (WDT) .................................................... 234 Associated Registers ................................................ 235 Clock Source............................................................. 234 Modes ....................................................................... 234 Period........................................................................ 234 Specifications............................................................ 269 WCOL bit .......................................................................... 195 WDTCON Register ........................................................... 235 WPUB Register ................................................................... 55 Write Collision Detect bit (WCOL)..................................... 195 WWW Address.................................................................. 325 WWW, On-Line Support ..................................................... 13
(c) 2007 Microchip Technology Inc.
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NOTES:
DS41250F-page 324
(c) 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
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DS41250F-page 325
PIC16F913/914/916/917/946
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS41250F FAX: (______) _________ - _________
Device: PIC16F913/914/916/917/946 Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41250F-page 326
(c) 2007 Microchip Technology Inc.
PIC16F917/916/914/913
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b) Device: PIC16F913, PIC16F913T(1) PIC16F914, PIC16F914T(1) PIC16F916, PIC16F916T(1) PIC16F917, PIC16F917T(1) PIC16F946, PIC16F946T(1) I E ML P PT SO SP SS = = = = = = = = -40C to +85C -40C to +125C Micro Lead Frame (QFN) Plastic DIP TQFP (Thin Quad Flatpack) SOIC Skinny Plastic DIP SSOP PIC16F913-E/SP 301 = Extended Temp., skinny PDIP package, 20 MHz, QTP pattern #301 PIC16F913-I/SO = Industrial Temp., SOIC package, 20 MHz
Temperature Range: Package:
Note 1:
T
= In tape and reel.
Pattern:
3-Digit Pattern Code for QTP (blank otherwise)
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type.
(c) 2007 Microchip Technology Inc.
DS41250F-page 327
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256
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EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
12/08/06
DS41250F-page 328
(c) 2007 Microchip Technology Inc.

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